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https://github.com/openwrt/openwrt.git
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b4c02c9998
Removed upstreamed patches:
generic/pending-5.4
445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch
446-mtd-spinand-gigadevice-Add-QE-Bit.patch
pistachio/patches-5.4
150-pwm-img-Fix-null-pointer-access-in-probe.patch
Manually rebased:
layerscape/patches-5.4
801-audio-0011-Revert-ASoC-fsl_sai-add-of_match-data.patch
801-audio-0039-MLK-16224-6-ASoC-fsl_sai-fix-DSD-suspend-resume.patch
801-audio-0073-MLK-21957-3-ASoC-fsl_sai-add-bitcount-and-timestamp-.patch
820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh.patch
All modifications made by update_kernel.sh
Build system: x86_64
Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711,
mvebu (mamba, rango), x86_64, ramips/mt7621
Run-tested: ipq806x/R7800, mvebu (mamba, rango), x86_64, ramips (RT-AC57U)
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
[alter 820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
80 lines
2.9 KiB
Diff
80 lines
2.9 KiB
Diff
From 9a379dd76a0369c09f1b613bdd869b6b0354a0f3 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.org>
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Date: Wed, 31 Oct 2018 14:57:21 +0000
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Subject: [PATCH] media: tc358743: Add support for 972Mbit/s link freq.
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Adds register setups for running the CSI lanes at 972Mbit/s,
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which allows 1080P50 UYVY down 2 lanes.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
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---
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drivers/media/i2c/tc358743.c | 47 +++++++++++++++++++++++++-----------
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1 file changed, 33 insertions(+), 14 deletions(-)
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--- a/drivers/media/i2c/tc358743.c
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+++ b/drivers/media/i2c/tc358743.c
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@@ -1978,6 +1978,7 @@ static int tc358743_probe_of(struct tc35
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/*
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* The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
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* The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
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+ * 972 Mbps allows 1080P50 UYVY over 2-lane.
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*/
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bps_pr_lane = 2 * endpoint.link_frequencies[0];
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if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
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@@ -1990,23 +1991,41 @@ static int tc358743_probe_of(struct tc35
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state->pdata.refclk_hz * state->pdata.pll_prd;
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/*
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- * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
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- * link frequency). In principle it should be possible to calculate
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+ * FIXME: These timings are from REF_02 for 594 or 972 Mbps per lane
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+ * (297 MHz or 486 MHz link frequency).
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+ * In principle it should be possible to calculate
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* them based on link frequency and resolution.
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*/
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- if (bps_pr_lane != 594000000U)
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+ switch (bps_pr_lane) {
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+ default:
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dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
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- state->pdata.lineinitcnt = 0xe80;
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- state->pdata.lptxtimecnt = 0x003;
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- /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
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- state->pdata.tclk_headercnt = 0x1403;
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- state->pdata.tclk_trailcnt = 0x00;
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- /* ths-preparecnt: 3, ths-zerocnt: 1 */
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- state->pdata.ths_headercnt = 0x0103;
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- state->pdata.twakeup = 0x4882;
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- state->pdata.tclk_postcnt = 0x008;
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- state->pdata.ths_trailcnt = 0x2;
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- state->pdata.hstxvregcnt = 0;
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+ case 594000000U:
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+ state->pdata.lineinitcnt = 0xe80;
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+ state->pdata.lptxtimecnt = 0x003;
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+ /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
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+ state->pdata.tclk_headercnt = 0x1403;
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+ state->pdata.tclk_trailcnt = 0x00;
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+ /* ths-preparecnt: 3, ths-zerocnt: 1 */
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+ state->pdata.ths_headercnt = 0x0103;
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+ state->pdata.twakeup = 0x4882;
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+ state->pdata.tclk_postcnt = 0x008;
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+ state->pdata.ths_trailcnt = 0x2;
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+ state->pdata.hstxvregcnt = 0;
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+ break;
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+ case 972000000U:
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+ state->pdata.lineinitcnt = 0x1b58;
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+ state->pdata.lptxtimecnt = 0x007;
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+ /* tclk-preparecnt: 6, tclk-zerocnt: 40 */
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+ state->pdata.tclk_headercnt = 0x2806;
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+ state->pdata.tclk_trailcnt = 0x00;
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+ /* ths-preparecnt: 6, ths-zerocnt: 8 */
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+ state->pdata.ths_headercnt = 0x0806;
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+ state->pdata.twakeup = 0x4268;
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+ state->pdata.tclk_postcnt = 0x008;
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+ state->pdata.ths_trailcnt = 0x5;
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+ state->pdata.hstxvregcnt = 0;
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+ break;
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+ }
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state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
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GPIOD_OUT_LOW);
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