mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 07:22:33 +00:00
3b53d6fdbc
The IRQ init structs are marked as __initconst which means this memory can be free after init. On this platform, the PCI IRQ init happens very late _after_ the kernel already freed the memory allocated for these structs. During IRQ allocation, the allocation function is passed with invalid data at this point leading to following error: [ 0.000000] SoC: Qualcomm Atheros QCA9533 ver 2 rev 0 [ 2.382828] Freeing unused kernel memory: 264K [ 34.414816] pci 0000:00:00.0: no irq found for pin 1 and [ 0.000000] SoC: Qualcomm Atheros QCA956X ver 1 rev 0 [ 2.125401] Freeing unused kernel memory: 284K [ 9.526479] pci 0000:00:00.0: no irq found for pin 1 After this patch: [ 14.960814] pci 0000:00:00.0: using irq 40 for pin 1 Commit318e19ba67("ar71xx: add v4.14 support") fixed this for the default targets already present in the source by default but forgot to remove the __initconst attribute for targets QCA953x and QCA956x which are only added later through platform patches. Fixes:318e19ba67("ar71xx: add v4.14 support") Reported-by: Sven Schönhoff <sven.schoenhoff@gmail.com> Reported-by: Dirk Brenken <dev@brenken.org> Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com> Tested-by: Dirk Brenken <dev@brenken.org>
45 lines
1.3 KiB
Diff
45 lines
1.3 KiB
Diff
--- a/arch/mips/ath79/pci.c
|
|
+++ b/arch/mips/ath79/pci.c
|
|
@@ -53,6 +53,15 @@ static const struct ath79_pci_irq ar724x
|
|
}
|
|
};
|
|
|
|
+static const struct ath79_pci_irq qca953x_pci_irq_map[] = {
|
|
+ {
|
|
+ .bus = 0,
|
|
+ .slot = 0,
|
|
+ .pin = 1,
|
|
+ .irq = ATH79_PCI_IRQ(0),
|
|
+ },
|
|
+};
|
|
+
|
|
static const struct ath79_pci_irq qca955x_pci_irq_map[] = {
|
|
{
|
|
.bus = 0,
|
|
@@ -98,6 +107,9 @@ int pcibios_map_irq(const struct pci_dev
|
|
soc_is_ar9344()) {
|
|
ath79_pci_irq_map = ar724x_pci_irq_map;
|
|
ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
|
|
+ } else if (soc_is_qca953x()) {
|
|
+ ath79_pci_irq_map = qca953x_pci_irq_map;
|
|
+ ath79_pci_nr_irqs = ARRAY_SIZE(qca953x_pci_irq_map);
|
|
} else if (soc_is_qca955x()) {
|
|
ath79_pci_irq_map = qca955x_pci_irq_map;
|
|
ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
|
|
@@ -303,6 +315,15 @@ int __init ath79_register_pci(void)
|
|
AR724X_PCI_MEM_SIZE,
|
|
0,
|
|
ATH79_IP2_IRQ(0));
|
|
+ } else if (soc_is_qca9533()) {
|
|
+ pdev = ath79_register_pci_ar724x(0,
|
|
+ QCA953X_PCI_CFG_BASE0,
|
|
+ QCA953X_PCI_CTRL_BASE0,
|
|
+ QCA953X_PCI_CRP_BASE0,
|
|
+ QCA953X_PCI_MEM_BASE0,
|
|
+ QCA953X_PCI_MEM_SIZE,
|
|
+ 0,
|
|
+ ATH79_IP2_IRQ(0));
|
|
} else if (soc_is_qca9558()) {
|
|
pdev = ath79_register_pci_ar724x(0,
|
|
QCA955X_PCI_CFG_BASE0,
|