mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-25 08:21:14 +00:00
b6da10f2d1
U-Boot 2021.10 has been released. Rebase mediatek patches on top of new release and remove some patches which have been merged upstream. Tested on Bananapi BPi-R2 (mt7623), Bananapi BPi-R64 (mt7622) and Linksys E8450 (mt7622). Signed-off-by: Daniel Golle <daniel@makrotopia.org>
454 lines
13 KiB
Diff
454 lines
13 KiB
Diff
--- /dev/null
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+++ b/configs/mt7622_ubnt_unifi-6-lr_defconfig
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@@ -0,0 +1,140 @@
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+CONFIG_ARM=y
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+CONFIG_POSITION_INDEPENDENT=y
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+CONFIG_ARCH_MEDIATEK=y
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+CONFIG_TARGET_MT7622=y
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+CONFIG_SYS_TEXT_BASE=0x41e00000
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+CONFIG_SYS_MALLOC_F_LEN=0x4000
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+CONFIG_USE_DEFAULT_ENV_FILE=y
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+CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:128k(bl2),640k(fip),64k(u-boot-env),256k(factory),64k(eeprom),15232k(recovery),-(firmware)"
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+CONFIG_ENV_IS_IN_MTD=y
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+CONFIG_ENV_MTD_NAME="nor0"
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+CONFIG_ENV_SIZE_REDUND=0x4000
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+CONFIG_ENV_SIZE=0x4000
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+CONFIG_ENV_OFFSET=0xc0000
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+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
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+CONFIG_BOARD_LATE_INIT=y
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+CONFIG_RESET_BUTTON_SETTLE_DELAY=400
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+CONFIG_BOOTP_SEND_HOSTNAME=y
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+CONFIG_DEFAULT_ENV_FILE="ubnt_unifi-6-lr_env"
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+CONFIG_DEBUG_UART_BASE=0x11002000
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+CONFIG_DEBUG_UART_CLOCK=25000000
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+CONFIG_DEFAULT_DEVICE_TREE="mt7622-ubnt-unifi-6-lr"
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+CONFIG_DEBUG_UART=y
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+CONFIG_SMBIOS_PRODUCT_NAME=""
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+CONFIG_AUTOBOOT_KEYED=y
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+CONFIG_BOOTDELAY=30
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+CONFIG_AUTOBOOT_MENU_SHOW=y
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+CONFIG_CFB_CONSOLE_ANSI=y
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+CONFIG_BUTTON=y
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+CONFIG_BUTTON_GPIO=y
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+CONFIG_GPIO_HOG=y
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+CONFIG_CMD_ENV_FLAGS=y
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+CONFIG_FIT=y
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+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
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+CONFIG_LOGLEVEL=7
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+CONFIG_LOG=y
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+CONFIG_DEFAULT_FDT_FILE="mt7622-ubnt-unifi-6-lr"
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+CONFIG_SYS_PROMPT="MT7622> "
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+# CONFIG_LEGACY_IMAGE_FORMAT is not set
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+# CONFIG_BOOTM_PLAN9 is not set
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+# CONFIG_BOOTM_RTEMS is not set
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+# CONFIG_BOOTM_VXWORKS is not set
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+# CONFIG_EFI is not set
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+# CONFIG_EFI_LOADER is not set
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+CONFIG_CMD_BOOTMENU=y
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+# CONFIG_CMD_BOOTEFI is not set
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+CONFIG_CMD_BOOTP=y
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+CONFIG_CMD_BUTTON=y
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+CONFIG_CMD_CDP=y
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+CONFIG_CMD_DHCP=y
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+CONFIG_CMD_DNS=y
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+CONFIG_CMD_ECHO=y
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+# CONFIG_CMD_ELF is not set
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+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
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+CONFIG_CMD_ENV_READMEM=y
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+CONFIG_CMD_ERASEENV=y
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+CONFIG_CMD_GPIO=y
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+CONFIG_CMD_HASH=y
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+CONFIG_CMD_ITEST=y
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+CONFIG_CMD_LED=y
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+CONFIG_CMD_LINK_LOCAL=y
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+# CONFIG_CMD_MBR is not set
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+CONFIG_CMD_MTD=y
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+CONFIG_CMD_MTDPART=y
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+# CONFIG_CMD_PCI is not set
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+CONFIG_CMD_SF_TEST=y
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+CONFIG_CMD_PING=y
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+CONFIG_CMD_PXE=y
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+CONFIG_CMD_SMC=y
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+CONFIG_CMD_TFTPBOOT=y
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+CONFIG_CMD_TFTPSRV=y
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+# CONFIG_CMD_UNLZ4 is not set
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+CONFIG_CMD_ASKENV=y
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+CONFIG_CMD_PSTORE=y
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+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
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+CONFIG_CMD_RARP=y
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+CONFIG_CMD_SETEXPR=y
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+CONFIG_CMD_SLEEP=y
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+CONFIG_CMD_SOURCE=y
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+CONFIG_CMD_UUID=y
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+CONFIG_DISPLAY_CPUINFO=y
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+CONFIG_DM_ETH=y
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+CONFIG_DM_ETH_PHY=y
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+CONFIG_DM_GPIO=y
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+CONFIG_DM_MDIO=y
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+CONFIG_DM_MTD=y
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+CONFIG_DM_REGULATOR=y
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+CONFIG_DM_REGULATOR_FIXED=y
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+CONFIG_DM_REGULATOR_GPIO=y
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+# CONFIG_DM_MMC is not set
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+CONFIG_DM_SERIAL=y
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+CONFIG_DM_SPI=y
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+CONFIG_DM_SPI_FLASH=y
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+CONFIG_HUSH_PARSER=y
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+# CONFIG_PARTITION_UUIDS is not set
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+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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+# CONFIG_LED is not set
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+# CONFIG_LZ4 is not set
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+CONFIG_VERSION_VARIABLE=y
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+CONFIG_NETCONSOLE=y
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+CONFIG_REGMAP=y
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+CONFIG_SYSCON=y
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+CONFIG_CLK=y
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+CONFIG_PHY=y
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+CONFIG_PHY_FIXED=y
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+CONFIG_PHYLIB_10G=y
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+CONFIG_PHY_AQUANTIA=y
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+CONFIG_PHY_ADDR_ENABLE=y
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+CONFIG_PHY_ADDR=8
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+CONFIG_MEDIATEK_ETH=y
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+CONFIG_MTD=y
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+# CONFIG_MMC is not set
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+CONFIG_PINCTRL=y
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+CONFIG_PINCONF=y
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+CONFIG_PINCTRL_MT7622=y
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+CONFIG_POWER_DOMAIN=y
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+CONFIG_PRE_CONSOLE_BUFFER=y
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+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
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+CONFIG_MTK_POWER_DOMAIN=y
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+CONFIG_RAM=y
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+CONFIG_MTK_SERIAL=y
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+CONFIG_SPI=y
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+CONFIG_MTK_SNFI_SPI=y
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+CONFIG_MTK_SNOR=y
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+CONFIG_SYSRESET_WATCHDOG=y
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+CONFIG_WDT_MTK=y
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+CONFIG_HEXDUMP=y
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+CONFIG_RANDOM_UUID=y
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+CONFIG_REGEX=y
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+CONFIG_SPI_FLASH=y
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+CONFIG_SPI_FLASH_BAR=y
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+CONFIG_SPI_FLASH_MTD=y
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+CONFIG_SPI_FLASH_UNLOCK_ALL=y
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+CONFIG_SPI_FLASH_EON=y
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+CONFIG_SPI_FLASH_GIGADEVICE=y
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+CONFIG_SPI_FLASH_MACRONIX=y
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+CONFIG_SPI_FLASH_SPANSION=y
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+CONFIG_SPI_FLASH_STMICRO=y
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+CONFIG_SPI_FLASH_SST=y
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+CONFIG_SPI_FLASH_WINBOND=y
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+CONFIG_SPI_FLASH_XMC=y
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--- /dev/null
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+++ b/arch/arm/dts/mt7622-ubnt-unifi-6-lr.dts
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@@ -0,0 +1,202 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (c) 2019 MediaTek Inc.
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+ * Author: Sam Shih <sam.shih@mediatek.com>
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+ */
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+
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+/dts-v1/;
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+#include "mt7622.dtsi"
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+#include "mt7622-u-boot.dtsi"
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+
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+/ {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ model = "mt7622-ubnt-unifi-6-lr";
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+ compatible = "mediatek,mt7622", "ubnt,unifi-6-lr";
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+
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+ chosen {
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+ stdout-path = &uart0;
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+ tick-timer = &timer0;
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+ };
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+
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+ aliases {
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+ spi0 = &snor;
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+ };
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+
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+ gpio-keys {
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+ compatible = "gpio-keys";
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+ u-boot,dm-pre-reloc;
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+
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+ reset {
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+ label = "reset";
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+ gpios = <&gpio 62 GPIO_ACTIVE_LOW>;
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+ u-boot,dm-pre-reloc;
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+ };
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+ };
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+
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+ memory@40000000 {
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+ device_type = "memory";
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+ reg = <0x40000000 0x20000000>;
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+ };
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+
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+ reg_1p8v: regulator-1p8v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-1.8V";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+
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+ reg_3p3v: regulator-3p3v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-3.3V";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+
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+ reg_5v: regulator-5v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-5V";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+};
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+
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+&pcie {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
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+ status = "okay";
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+
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+ pcie@0,0 {
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+ status = "okay";
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+ };
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+
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+ pcie@1,0 {
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+ status = "okay";
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+ };
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+};
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+
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+&pinctrl {
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+ eth_pins: eth-pins {
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+ mux {
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+ function = "eth";
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+ groups = "mdc_mdio", "rgmii_via_gmac2";
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+ };
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+ };
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+
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+ pcie0_pins: pcie0-pins {
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+ mux {
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+ function = "pcie";
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+ groups = "pcie0_pad_perst",
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+ "pcie0_1_waken",
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+ "pcie0_1_clkreq";
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+ };
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+ };
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+
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+ pcie1_pins: pcie1-pins {
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+ mux {
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+ function = "pcie";
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+ groups = "pcie1_pad_perst",
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+ "pcie1_0_waken",
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+ "pcie1_0_clkreq";
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+ };
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+ };
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+
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+ snfi_pins: snfi-pins {
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+ mux {
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+ function = "flash";
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+ groups = "snfi";
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+ };
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+ };
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+
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+ snor_pins: snor-pins {
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+ mux {
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+ function = "flash";
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+ groups = "spi_nor";
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+ };
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+ };
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+
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+ uart0_pins: uart0 {
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+ mux {
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+ function = "uart";
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+ groups = "uart0_0_tx_rx" ;
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+ };
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+ };
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+
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+ watchdog_pins: watchdog-default {
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+ mux {
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+ function = "watchdog";
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+ groups = "watchdog";
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+ };
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+ };
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+};
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+
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+&snfi {
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+ pinctrl-names = "default", "snfi";
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+ pinctrl-0 = <&snor_pins>;
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+ pinctrl-1 = <&snfi_pins>;
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+ status = "okay";
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+
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+ spi-flash@0 {
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+ compatible = "jedec,spi-nor";
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+ reg = <0>;
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+ u-boot,dm-pre-reloc;
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+ };
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+};
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+
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+&snor {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&snor_pins>;
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+ status = "okay";
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+
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+ spi-flash@0 {
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+ compatible = "jedec,spi-nor";
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+ reg = <0>;
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+ spi-tx-bus-width = <1>;
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+ spi-rx-bus-width = <4>;
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+ u-boot,dm-pre-reloc;
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+ };
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+};
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+
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+&uart0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart0_pins>;
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+ status = "okay";
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+};
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+
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+&watchdog {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&watchdog_pins>;
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+ status = "okay";
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+};
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+
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+ð {
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+ status = "okay";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <ð_pins>;
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+
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+ mediatek,gmac-id = <0>;
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+ phy-mode = "sgmii";
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+ phy-handle = <&gphy>;
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+
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+ mdio-bus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ gphy: ethernet-phy@8 {
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+ /* Marvell AQRate AQR112W - no driver */
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ reg = <0x8>;
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+ };
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+ };
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+};
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -1105,6 +1105,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt7623a-unielec-u7623-02-emmc.dtb \
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mt7622-bananapi-bpi-r64.dtb \
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mt7622-linksys-e8450-ubi.dtb \
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+ mt7622-ubnt-unifi-6-lr.dtb \
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mt7623n-bananapi-bpi-r2.dtb \
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mt7629-rfb.dtb \
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mt8183-pumpkin.dtb \
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--- /dev/null
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+++ b/ubnt_unifi-6-lr_env
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@@ -0,0 +1,50 @@
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+ethaddr_factory=mtd read nor0 $loadaddr 0x110000 0x10000 && env readmem -b ethaddr $loadaddr 0x6 ; setenv ethaddr_factory
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+ipaddr=192.168.1.1
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+serverip=192.168.1.254
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+loadaddr=0x48000000
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+bootcmd=if pstore check ; then run boot_recovery ; else run boot_nor ; fi
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+bootdelay=0
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+bootfile=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-ubootmod-initramfs-recovery.itb
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+bootfile_bl2=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-ubootmod-preloader.bin
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+bootfile_fip=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-ubootmod-bl31-uboot.fip
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+bootfile_upg=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-ubootmod-squashfs-sysupgrade.itb
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+bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
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+bootmenu_default=0
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+bootmenu_delay=0
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+bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) )[0m
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+bootmenu_0=Initialize environment.=run _firstboot
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+bootmenu_0d=Run default boot command.=run boot_default
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+bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
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+bootmenu_2=Boot production system from flash.=run boot_production ; run bootmenu_confirm_return
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+bootmenu_3=Boot recovery system from flash.=run boot_recovery ; run bootmenu_confirm_return
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+bootmenu_4=Load production system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
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+bootmenu_5=Load recovery system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
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+bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to flash.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return
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+bootmenu_7=[31mLoad BL2 preloader via TFTP then write to flash.[0m=run boot_tftp_write_preloader ; run bootmenu_confirm_return
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+bootmenu_8=Reboot.=reset
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+bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
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+boot_first=if button reset ; then run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
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+boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
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+boot_production=run nor_read_production && bootm $loadaddr
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+boot_recovery=run nor_read_recovery ; bootm $loadaddr
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+boot_serial_write_fip=loadx $loadaddr 115200 && run boot_write_fip
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+boot_serial_write_preloader=loadx $loadaddr 115200 && run boot_write_preloader
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+boot_tftp_forever=while true ; do run boot_tftp_recovery ; sleep 1 ; done
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+boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run nor_write_production ; if env exists noboot ; then else bootm $loadaddr ; fi
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+boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run nor_write_recovery ; if env exists noboot ; then else bootm $loadaddr ; fi
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+boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr
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+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip
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+boot_tftp_write_preloader=tftpboot $loadaddr $bootfile_bl2 && run boot_write_preloader
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+boot_nor=run boot_production ; run boot_recovery
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+boot_write_fip=mtd erase nor0 0x20000 0x80000 && mtd write nor0 $loadaddr 0x20000 0x80000
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+boot_write_preloader=mtd erase nor0 0x0 0x20000 && mtd write nor0 $loadaddr 0x0 0x20000
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+reset_factory=mtd erase nor0 0xc0000 0x10000 && reset
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+nor_read_production=mtd read nor0 $loadaddr 0x1000000 0x1000 && imsz $loadaddr image_size && mtd read nor0 $loadaddr 0x1000000 $image_size
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+nor_read_recovery=mtd read nor0 $loadaddr 0x120000 0x1000 && imsz $loadaddr image_size && mtd read nor0 $loadaddr 0x120000 $image_size
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+nor_pad_size=imsz $loadaddr image_size ; setexpr image_eb $image_size / 0x1000 ; setexpr tmp1 image_size % 0x1000 ; test 0x$tmp1 -gt 0 && setexpr image_eb $image_eb + 1 ; setexpr image_eb $image_eb * 0x1000
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+nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0x3000000 && mtd erase nor0 0x1000000 0x$image_eb && mtd write nor0 $loadaddr 0x1000000 $filesize
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+nor_write_recovery=run nor_pad_size ; test 0x$image_eb -le 0xee0000 && mtd erase nor0 0x120000 0x$image_eb && mtd write nor0 $loadaddr 0x120000 $filesize
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+_init_env=setenv _init_env ; saveenv
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+_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run _init_env ; run boot_first
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+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
|
||
+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m"
|
||
--- a/common/board_r.c
|
||
+++ b/common/board_r.c
|
||
@@ -77,6 +77,7 @@
|
||
#ifdef CONFIG_EFI_SETUP_EARLY
|
||
#include <efi_loader.h>
|
||
#endif
|
||
+#include <spi_flash.h>
|
||
|
||
DECLARE_GLOBAL_DATA_PTR;
|
||
|
||
@@ -416,6 +417,21 @@ static int initr_onenand(void)
|
||
}
|
||
#endif
|
||
|
||
+#if defined(CONFIG_SPI_FLASH)
|
||
+/* probe SPI FLASH */
|
||
+static int initr_spiflash(void)
|
||
+{
|
||
+ struct udevice *new;
|
||
+
|
||
+ spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS,
|
||
+ CONFIG_SF_DEFAULT_CS,
|
||
+ CONFIG_SF_DEFAULT_SPEED,
|
||
+ CONFIG_SF_DEFAULT_MODE,
|
||
+ &new);
|
||
+ return 0;
|
||
+}
|
||
+#endif
|
||
+
|
||
#ifdef CONFIG_MMC
|
||
static int initr_mmc(void)
|
||
{
|
||
@@ -705,6 +721,9 @@ static init_fnc_t init_sequence_r[] = {
|
||
#ifdef CONFIG_CMD_ONENAND
|
||
initr_onenand,
|
||
#endif
|
||
+#ifdef CONFIG_SPI_FLASH
|
||
+ initr_spiflash,
|
||
+#endif
|
||
#ifdef CONFIG_MMC
|
||
initr_mmc,
|
||
#endif
|