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d16bd89c71
This solves issue with DDR training on Turris Omnia. Log: ******** DRAM initialization Failed (res 0x1) ******** DDR3 Training Sequence - FAILED ERROR ### Please RESET the board ### Signed-off-by: Josef Schlehofer <pepe.schlehofer@gmail.com>
99 lines
3.5 KiB
Diff
99 lines
3.5 KiB
Diff
From eadc4f512fb43bba2fa4e842c982da919da664be Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
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Date: Tue, 4 Jan 2022 15:57:49 +0100
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Subject: [PATCH] ddr: marvell: a38x: Fix Synchronous vs Asynchronous mode
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determination
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Before commit 4c289425752f ("mv_ddr: a38x: add support for ddr async
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mode"), Asynchornous Mode was only used when the CPU Subsystem Clock
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Options[4:0] field in the SAR1 register was set to value 0x13: CPU at
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2 GHz and DDR at 933 MHz.
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Then commit 4c289425752f ("mv_ddr: a38x: add support for ddr async
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mode") added support for Asynchornous Modes with frequencies other than
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933 MHz (but at least 467 MHz), but the code it added to check for
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whether Asynchornous Mode should be used is wrong: it checks whether the
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frequency setting in board DDR topology map is set to value other than
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MV_DDR_FREQ_SAR.
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Thus boards which define a specific value, greater than 400 MHz, for DDR
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frequency in their board topology (e.g. Turris Omnia defines
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MV_DDR_FREQ_800), are incorrectly put into Asynchornous Mode after that
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commit.
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The A38x Functional Specification, section 10.12 DRAM Clocking, says:
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In Synchornous mode, the DRAM and CPU clocks are edge aligned and run
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in 1:2 or 1:3 CPU to DRAM frequency ratios.
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Change the check for whether Asynchornous Mode should be used according
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to this explanation in Functional Specification.
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Signed-off-by: Marek Behún <marek.behun@nic.cz>
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Tested-by: Chris Packham <judge.packham@gmail.com>
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Reviewed-by: Stefan Roese <sr@denx.de>
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---
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drivers/ddr/marvell/a38x/mv_ddr_plat.c | 19 ++++++++-----------
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1 file changed, 8 insertions(+), 11 deletions(-)
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--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c
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+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
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@@ -167,8 +167,6 @@ static u16 a38x_vco_freq_per_sar_ref_clk
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};
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-static u32 async_mode_at_tf;
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-
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static u32 dq_bit_map_2_phy_pin[] = {
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1, 0, 2, 6, 9, 8, 3, 7, /* 0 */
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8, 9, 1, 7, 2, 6, 3, 0, /* 1 */
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@@ -734,7 +732,8 @@ static int ddr3_tip_a38x_set_divider(u8
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u32 divider = 0;
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u32 sar_val, ref_clk_satr;
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u32 async_val;
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- u32 freq = mv_ddr_freq_get(frequency);
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+ u32 cpu_freq;
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+ u32 ddr_freq = mv_ddr_freq_get(frequency);
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if (if_id != 0) {
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DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR,
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@@ -751,11 +750,14 @@ static int ddr3_tip_a38x_set_divider(u8
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ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG);
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if (((ref_clk_satr >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) ==
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DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ)
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- divider = a38x_vco_freq_per_sar_ref_clk_25_mhz[sar_val] / freq;
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+ cpu_freq = a38x_vco_freq_per_sar_ref_clk_25_mhz[sar_val];
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else
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- divider = a38x_vco_freq_per_sar_ref_clk_40_mhz[sar_val] / freq;
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+ cpu_freq = a38x_vco_freq_per_sar_ref_clk_40_mhz[sar_val];
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+
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+ divider = cpu_freq / ddr_freq;
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- if ((async_mode_at_tf == 1) && (freq > 400)) {
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+ if (((cpu_freq % ddr_freq != 0) || (divider != 2 && divider != 3)) &&
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+ (ddr_freq > 400)) {
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/* Set async mode */
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dunit_write(0x20220, 0x1000, 0x1000);
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dunit_write(0xe42f4, 0x200, 0x200);
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@@ -869,8 +871,6 @@ int ddr3_tip_ext_write(u32 dev_num, u32
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int mv_ddr_early_init(void)
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{
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- struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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-
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/* FIXME: change this configuration per ddr type
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* configure a380 and a390 to work with receiver odt timing
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* the odt_config is defined:
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@@ -882,9 +882,6 @@ int mv_ddr_early_init(void)
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mv_ddr_sw_db_init(0, 0);
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- if (tm->interface_params[0].memory_freq != MV_DDR_FREQ_SAR)
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- async_mode_at_tf = 1;
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-
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return MV_OK;
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}
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