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c36de2e73a
Backport almost 50 commits from upstream Linux to improve thermal drivers for MediaTek SoCs and add new LVTS driver for MT7988. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
150 lines
5.4 KiB
Diff
150 lines
5.4 KiB
Diff
From 9aad43ad3285fc21158fb416830a6156a9a31fa5 Mon Sep 17 00:00:00 2001
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From: Balsam CHIHI <bchihi@baylibre.com>
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Date: Tue, 7 Mar 2023 16:45:22 +0100
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Subject: [PATCH 15/42] thermal/drivers/mediatek/lvts_thermal: Add AP domain
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for mt8195
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Add MT8195 AP Domain support to LVTS Driver.
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Take the opportunity to update the comments to show calibration data
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information related to the new domain.
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[dlezcano]: Massaged a bit the changelog
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Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
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Tested-by: Chen-Yu Tsai <wenst@chromium.org>
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Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Link: https://lore.kernel.org/r/20230307154524.118541-3-bchihi@baylibre.com
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---
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drivers/thermal/mediatek/lvts_thermal.c | 94 +++++++++++++++++++------
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1 file changed, 74 insertions(+), 20 deletions(-)
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--- a/drivers/thermal/mediatek/lvts_thermal.c
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+++ b/drivers/thermal/mediatek/lvts_thermal.c
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@@ -530,29 +530,33 @@ static int lvts_sensor_init(struct devic
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* The efuse blob values follows the sensor enumeration per thermal
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* controller. The decoding of the stream is as follow:
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*
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- * <--?-> <----big0 ???---> <-sensor0-> <-0->
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- * ------------------------------------------
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- * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 |
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- * ------------------------------------------
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+ * stream index map for MCU Domain :
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*
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- * <--sensor1--><-0-> <----big1 ???---> <-sen
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- * ------------------------------------------
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- * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
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- * ------------------------------------------
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+ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
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+ * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
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*
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- * sor0-> <-0-> <-sensor1-> <-0-> ..........
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- * ------------------------------------------
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- * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
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- * ------------------------------------------
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+ * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3----->
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+ * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12
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*
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- * And so on ...
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+ * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
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+ * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
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+ *
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+ * stream index map for AP Domain :
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+ *
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+ * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
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+ * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
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+ *
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+ * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3----->
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+ * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
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+ *
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+ * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6----->
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+ * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F
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+ *
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+ * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8----->
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+ * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48
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*
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* The data description gives the offset of the calibration data in
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* this bytes stream for each sensor.
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- *
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- * Each thermal controller can handle up to 4 sensors max, we don't
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- * care if there are less as the array of calibration is sized to 4
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- * anyway. The unused sensor slot will be zeroed.
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*/
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static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
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const struct lvts_ctrl_data *lvts_ctrl_data,
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@@ -1165,7 +1169,7 @@ static int lvts_remove(struct platform_d
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return 0;
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}
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-static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = {
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+static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
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{
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.cal_offset = { 0x04, 0x07 },
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.lvts_sensor = {
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@@ -1200,13 +1204,63 @@ static const struct lvts_ctrl_data mt819
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}
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};
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+static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
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+ {
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+ .cal_offset = { 0x25, 0x28 },
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+ .lvts_sensor = {
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+ { .dt_id = MT8195_AP_VPU0 },
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+ { .dt_id = MT8195_AP_VPU1 }
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+ },
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+ .num_lvts_sensor = 2,
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+ .offset = 0x0,
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+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
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+ },
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+ {
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+ .cal_offset = { 0x2e, 0x31 },
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+ .lvts_sensor = {
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+ { .dt_id = MT8195_AP_GPU0 },
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+ { .dt_id = MT8195_AP_GPU1 }
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+ },
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+ .num_lvts_sensor = 2,
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+ .offset = 0x100,
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+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
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+ },
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+ {
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+ .cal_offset = { 0x37, 0x3a, 0x3d },
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+ .lvts_sensor = {
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+ { .dt_id = MT8195_AP_VDEC },
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+ { .dt_id = MT8195_AP_IMG },
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+ { .dt_id = MT8195_AP_INFRA },
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+ },
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+ .num_lvts_sensor = 3,
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+ .offset = 0x200,
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+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
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+ },
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+ {
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+ .cal_offset = { 0x43, 0x46 },
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+ .lvts_sensor = {
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+ { .dt_id = MT8195_AP_CAM0 },
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+ { .dt_id = MT8195_AP_CAM1 }
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+ },
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+ .num_lvts_sensor = 2,
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+ .offset = 0x300,
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+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
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+ }
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+};
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+
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static const struct lvts_data mt8195_lvts_mcu_data = {
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- .lvts_ctrl = mt8195_lvts_data_ctrl,
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- .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_data_ctrl),
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+ .lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
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+ .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
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+};
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+
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+static const struct lvts_data mt8195_lvts_ap_data = {
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+ .lvts_ctrl = mt8195_lvts_ap_data_ctrl,
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+ .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
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};
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static const struct of_device_id lvts_of_match[] = {
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{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
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+ { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
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{},
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};
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MODULE_DEVICE_TABLE(of, lvts_of_match);
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