openwrt/target/linux/mediatek/dts/mt7981b-cudy-wr3000-v1.dts
Chukun Pan 99bc8a9770 mediatek: Cudy WR3000: simplify mac address setup
The mac address of the network port under the switch is
the same as the corresponding gmac by default, so there
is no need to repeat the setting. Compile test only.

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
2024-01-14 23:11:57 +00:00

275 lines
4.2 KiB
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
#include "mt7981.dtsi"
/ {
model = "Cudy WR3000 v1";
compatible = "cudy,wr3000-v1", "mediatek,mt7981";
aliases {
ethernet0 = &gmac0;
label-mac-device = &gmac0;
led-boot = &led_status;
led-failsafe = &led_status;
led-running = &led_status;
led-upgrade = &led_status;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
};
};
leds {
compatible = "gpio-leds";
led_status: led@0 {
label = "blue:status";
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
led@1 {
label = "blue:internet";
gpios = <&pio 11 GPIO_ACTIVE_LOW>;
};
led@2 {
label = "blue:wan";
gpios = <&pio 5 GPIO_ACTIVE_LOW>;
};
led@3 {
label = "blue:lan";
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
led@4 {
label = "blue:wifi2";
gpios = <&pio 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
led@5 {
label = "blue:wifi5";
gpios = <&pio 7 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
};
};
&uart0 {
status = "okay";
};
&watchdog {
status = "okay";
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_bdinfo_de00 0>;
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
status = "disabled";
};
};
&mdio_bus {
switch: switch@1f {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_flash_pins>;
status = "disabled";
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_flash_pins>;
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@00000 {
label = "BL2";
reg = <0x00000 0x40000>;
read-only;
};
partition@40000 {
label = "u-boot-env";
reg = <0x40000 0x10000>;
read-only;
};
factory: partition@50000 {
label = "Factory";
reg = <0x50000 0x10000>;
read-only;
};
bdinfo: partition@60000 {
label = "bdinfo";
reg = <0x60000 0x10000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_bdinfo_de00: macaddr@de00 {
compatible = "mac-base";
reg = <0xde00 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
partition@70000 {
label = "FIP";
reg = <0x70000 0x80000>;
read-only;
};
partition@f0000 {
compatible = "denx,fit";
label = "firmware";
reg = <0xf0000 0xf10000>;
};
};
};
};
&pio {
spi0_flash_pins: spi0-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
spi2_flash_pins: spi2-pins {
mux {
function = "spi";
groups = "spi2", "spi2_wp_hold";
};
conf-pu {
pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
drive-strength = <8>;
bias-pull-up = <103>;
};
conf-pd {
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
drive-strength = <8>;
bias-pull-down = <103>;
};
};
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "wan";
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_bdinfo_de00 1>;
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&wifi {
status = "okay";
mediatek,mtd-eeprom = <&factory 0x0>;
};