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e2e2fc3cd0
Add updated patches for 6.6. DMA/cache-handling patches have been reworked / backported from upstream. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
50 lines
1.5 KiB
Diff
50 lines
1.5 KiB
Diff
From 7be159c760aa8a1ece1354892af215b2f8c21152 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Date: Thu, 30 Nov 2023 16:19:30 +0100
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Subject: [PATCH 1021/1024] riscv: dts: starfive: Add JH7100 MMC nodes
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Add device tree nodes for the Synopsis MMC controllers on the
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StarFive JH7100 SoC.
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Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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---
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arch/riscv/boot/dts/starfive/jh7100.dtsi | 26 ++++++++++++++++++++++++
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1 file changed, 26 insertions(+)
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--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
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+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
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@@ -188,6 +188,32 @@
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#reset-cells = <1>;
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};
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+ sdio0: mmc@10000000 {
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+ compatible = "snps,dw-mshc";
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+ reg = <0x0 0x10000000 0x0 0x10000>;
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+ clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
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+ <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>;
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+ clock-names = "biu", "ciu";
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+ interrupts = <4>;
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+ data-addr = <0>;
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+ fifo-depth = <32>;
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+ fifo-watermark-aligned;
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+ status = "disabled";
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+ };
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+
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+ sdio1: mmc@10010000 {
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+ compatible = "snps,dw-mshc";
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+ reg = <0x0 0x10010000 0x0 0x10000>;
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+ clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
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+ <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>;
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+ clock-names = "biu", "ciu";
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+ interrupts = <5>;
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+ data-addr = <0>;
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+ fifo-depth = <32>;
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+ fifo-watermark-aligned;
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+ status = "disabled";
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+ };
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+
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clkgen: clock-controller@11800000 {
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compatible = "starfive,jh7100-clkgen";
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reg = <0x0 0x11800000 0x0 0x10000>;
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