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This change adds PCIe support to IPQ806x based platforms. The driver is actually cherry-picked from the following LKML thread: *https://lwn.net/Articles/643086/ (patches 110-111) We also add here an additional fix to support multiple PCI controllers on the same platform (patch 112), and to patch the ap148 & dbs149 DTS files (patch 113). Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 45663
267 lines
8.2 KiB
Diff
267 lines
8.2 KiB
Diff
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Subject: [v2,3/5] DT: PCI: qcom: Document PCIe devicetree bindings
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From: Stanimir Varbanov <svarbanov@mm-sol.com>
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X-Patchwork-Id: 6326181
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Message-Id: <1430743338-10441-4-git-send-email-svarbanov@mm-sol.com>
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To: Rob Herring <robh+dt@kernel.org>, Kumar Gala <galak@codeaurora.org>,
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Mark Rutland <mark.rutland@arm.com>,
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Grant Likely <grant.likely@linaro.org>,
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Bjorn Helgaas <bhelgaas@google.com>,
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Kishon Vijay Abraham I <kishon@ti.com>,
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Russell King <linux@arm.linux.org.uk>, Arnd Bergmann <arnd@arndb.de>
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Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
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linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
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linux-pci@vger.kernel.org, Mathieu Olivari <mathieu@codeaurora.org>,
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Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
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Stanimir Varbanov <svarbanov@mm-sol.com>
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Date: Mon, 4 May 2015 15:42:16 +0300
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Document Qualcomm PCIe driver devicetree bindings.
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Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
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---
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.../devicetree/bindings/pci/qcom,pcie.txt | 231 ++++++++++++++++++++
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1 files changed, 231 insertions(+), 0 deletions(-)
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create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.txt
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diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
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new file mode 100644
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index 0000000..dcf7348
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
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@@ -0,0 +1,231 @@
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+* Qualcomm PCI express root complex
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+
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+- compatible:
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+ Usage: required
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+ Value type: <stringlist>
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+ Definition: Value shall include
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+ - "qcom,pcie-v0" for apq/ipq8064
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+ - "qcom,pcie-v1" for apq8084
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+
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+- reg:
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+ Usage: required
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+ Value type: <prop-encoded-array>
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+ Definition: Register ranges as listed in the reg-names property
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+
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+- reg-names:
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+ Usage: required
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+ Value type: <stringlist>
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+ Definition: Must include the following entries
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+ - "parf" Qualcomm specific registers
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+ - "dbi" Designware PCIe registers
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+ - "elbi" External local bus interface registers
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+ - "config" PCIe configuration space
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+
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+- device_type:
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+ Usage: required
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+ Value type: <string>
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+ Definition: Should be "pci". As specified in designware-pcie.txt
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+
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+- #address-cells:
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+ Usage: required
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+ Value type: <u32>
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+ Definition: Should be set to 3. As specified in designware-pcie.txt
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+
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+- #size-cells:
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+ Usage: required
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+ Value type: <u32>
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+ Definition: Should be set 2. As specified in designware-pcie.txt
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+
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+- ranges:
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+ Usage: required
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+ Value type: <prop-encoded-array>
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+ Definition: As specified in designware-pcie.txt
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+
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+- interrupts:
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+ Usage: required
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+ Value type: <prop-encoded-array>
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+ Definition: MSI interrupt
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+
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+- interrupt-names:
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+ Usage: required
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+ Value type: <stringlist>
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+ Definition: Should contain "msi"
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+
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+- #interrupt-cells:
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+ Usage: required
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+ Value type: <u32>
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+ Definition: Should be 1. As specified in designware-pcie.txt
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+
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+- interrupt-map-mask:
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+ Usage: required
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+ Value type: <prop-encoded-array>
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+ Definition: As specified in designware-pcie.txt
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+
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+- interrupt-map:
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+ Usage: required
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+ Value type: <prop-encoded-array>
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+ Definition: As specified in designware-pcie.txt
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+
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+- clocks:
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+ Usage: required
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+ Value type: <prop-encoded-array>
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+ Definition: List of phandle and clock specifier pairs as listed
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+ in clock-names property
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+
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+- clock-names:
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+ Usage: required
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+ Value type: <stringlist>
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+ Definition: Should contain the following entries
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+ * should be populated for v0 and v1
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+ - "iface" Configuration AHB clock
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+
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+ * should be populated for v0
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+ - "core" Clocks the pcie hw block
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+ - "phy" Clocks the pcie PHY block
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+
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+ * should be populated for v1
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+ - "aux" Auxiliary (AUX) clock
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+ - "bus_master" Master AXI clock
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+ - "bus_slave" Slave AXI clock
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+
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+- resets:
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+ Usage: required
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+ Value type: <prop-encoded-array>
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+ Definition: List of phandle and reset specifier pairs as listed
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+ in reset-names property
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+
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+- reset-names:
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+ Usage: required
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+ Value type: <stringlist>
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+ Definition: Should contain the following entries
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+ * should be populated for v0
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+ - "axi" AXI reset
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+ - "ahb" AHB reset
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+ - "por" POR reset
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+ - "pci" PCI reset
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+ - "phy" PHY reset
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+
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+ * should be populated for v1
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+ - "core" Core reset
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+
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+- power-domains:
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+ Usage: required (for v1 only)
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+ Value type: <prop-encoded-array>
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+ Definition: A phandle and power domain specifier pair to the
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+ power domain which is responsible for collapsing
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+ and restoring power to the peripheral
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+
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+- <name>-supply:
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+ Usage: required
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+ Value type: <phandle>
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+ Definition: List of phandles to the power supply regulator(s)
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+ * should be populated for v0 and v1
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+ - "vdda" core analog power supply
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+
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+ * should be populated for v0
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+ - "vdda_phy" analog power supply for PHY
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+ - "vdda_refclk" analog power supply for IC which generate
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+ reference clock
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+
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+- phys:
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+ Usage: required (for v1 only)
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+ Value type: <phandle>
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+ Definition: List of phandle(s) as listed in phy-names property
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+
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+- phy-names:
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+ Usage: required (for v1 only)
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+ Value type: <stringlist>
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+ Definition: Should contain "pciephy"
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+
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+- <name>-gpio:
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+ Usage: optional
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+ Value type: <prop-encoded-array>
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+ Definition: List of phandle and gpio specifier pairs. Should contain
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+ - "perst" PCIe endpoint reset signal line
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+ - "pewake" PCIe endpoint wake signal line
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+
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+- pinctrl-0:
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+ Usage: required
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+ Value type: <phandle>
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+ Definition: List of phandles pointing at a pin(s) configuration
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+
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+- pinctrl-names
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+ Usage: required
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+ Value type: <stringlist>
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+ Definition: List of names of pinctrl-0 state
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+
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+* Example for v0
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+ pcie0: pci@1b500000 {
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+ compatible = "qcom,pcie-v0";
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+ reg = <0x1b500000 0x1000
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+ 0x1b502000 0x80
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+ 0x1b600000 0x100
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+ 0x0ff00000 0x100000>;
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+ reg-names = "dbi", "elbi", "parf", "config";
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+ device_type = "pci";
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+ linux,pci-domain = <0>;
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+ bus-range = <0x00 0xff>;
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+ num-lanes = <1>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
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+ 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* memory */
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+ interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
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+ interrupt-names = "msi";
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0x7>;
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+ interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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+ <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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+ <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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+ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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+ clocks = <&gcc PCIE_A_CLK>,
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+ <&gcc PCIE_H_CLK>,
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+ <&gcc PCIE_PHY_CLK>;
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+ clock-names = "core", "iface", "phy";
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+ resets = <&gcc PCIE_ACLK_RESET>,
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+ <&gcc PCIE_HCLK_RESET>,
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+ <&gcc PCIE_POR_RESET>,
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+ <&gcc PCIE_PCI_RESET>,
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+ <&gcc PCIE_PHY_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy";
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+ };
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+
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+* Example for v1
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+ pcie0@fc520000 {
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+ compatible = "qcom,pcie-v1";
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+ reg = <0xfc520000 0x2000>,
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+ <0xff000000 0x1000>,
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+ <0xff001000 0x1000>,
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+ <0xff002000 0x2000>;
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+ reg-names = "parf", "dbi", "elbi", "config";
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+ device_type = "pci";
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+ linux,pci-domain = <0>;
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+ bus-range = <0x00 0xff>;
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+ num-lanes = <1>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */
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+ 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
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+ interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
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+ interrupt-names = "msi";
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0x7>;
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+ interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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+ <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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+ <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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+ <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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+ clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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+ <&gcc GCC_PCIE_0_AUX_CLK>;
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+ clock-names = "iface", "master_bus", "slave_bus", "aux";
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+ resets = <&gcc GCC_PCIE_0_BCR>;
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+ reset-names = "core";
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+ power-domains = <&gcc PCIE0_GDSC>;
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+ vdda-supply = <&pma8084_l3>;
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+ phys = <&pciephy0>;
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+ phy-names = "pciephy";
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+ perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
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+ pinctrl-0 = <&pcie0_pins_default>;
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+ pinctrl-names = "default";
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+ };
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