mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 22:23:27 +00:00
f2f42a54e8
The qca8k patch series brings the numbering to 799. This patch renames 7xx patches to create space for more backports to be added. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> [rename 729->719] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
66 lines
2.4 KiB
Diff
66 lines
2.4 KiB
Diff
From bbc4799e8bb6c397e3b3fec13de68e179f5db9ff Mon Sep 17 00:00:00 2001
|
|
From: Ansuel Smith <ansuelsmth@gmail.com>
|
|
Date: Thu, 14 Oct 2021 00:39:13 +0200
|
|
Subject: net: dsa: qca8k: add explicit SGMII PLL enable
|
|
|
|
Support enabling PLL on the SGMII CPU port. Some device require this
|
|
special configuration or no traffic is transmitted and the switch
|
|
doesn't work at all. A dedicated binding is added to the CPU node
|
|
port to apply the correct reg on mac config.
|
|
Fail to correctly configure sgmii with qca8327 switch and warn if pll is
|
|
used on qca8337 with a revision greater than 1.
|
|
|
|
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
|
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
|
|
Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
---
|
|
drivers/net/dsa/qca8k.c | 19 +++++++++++++++++--
|
|
drivers/net/dsa/qca8k.h | 1 +
|
|
2 files changed, 18 insertions(+), 2 deletions(-)
|
|
|
|
--- a/drivers/net/dsa/qca8k.c
|
|
+++ b/drivers/net/dsa/qca8k.c
|
|
@@ -1002,6 +1002,18 @@ qca8k_parse_port_config(struct qca8k_pri
|
|
if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
|
|
priv->sgmii_rx_clk_falling_edge = true;
|
|
|
|
+ if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) {
|
|
+ priv->sgmii_enable_pll = true;
|
|
+
|
|
+ if (priv->switch_id == QCA8K_ID_QCA8327) {
|
|
+ dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling");
|
|
+ priv->sgmii_enable_pll = false;
|
|
+ }
|
|
+
|
|
+ if (priv->switch_revision < 2)
|
|
+ dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more.");
|
|
+ }
|
|
+
|
|
break;
|
|
default:
|
|
continue;
|
|
@@ -1312,8 +1324,11 @@ qca8k_phylink_mac_config(struct dsa_swit
|
|
if (ret)
|
|
return;
|
|
|
|
- val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
|
|
- QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
|
|
+ val |= QCA8K_SGMII_EN_SD;
|
|
+
|
|
+ if (priv->sgmii_enable_pll)
|
|
+ val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
|
|
+ QCA8K_SGMII_EN_TX;
|
|
|
|
if (dsa_is_cpu_port(ds, port)) {
|
|
/* CPU port, we're talking to the CPU MAC, be a PHY */
|
|
--- a/drivers/net/dsa/qca8k.h
|
|
+++ b/drivers/net/dsa/qca8k.h
|
|
@@ -266,6 +266,7 @@ struct qca8k_priv {
|
|
u8 switch_revision;
|
|
bool sgmii_rx_clk_falling_edge;
|
|
bool sgmii_tx_clk_falling_edge;
|
|
+ bool sgmii_enable_pll;
|
|
u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
|
|
u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
|
|
bool legacy_phy_port_mapping;
|