mirror of
https://github.com/openwrt/openwrt.git
synced 2025-01-17 10:20:01 +00:00
e58cd453d5
Add kernel support for SAMA7G5 by back-porting mainline kernel patches. Among SAMA7G5 features could be remembered: - ARM Cortex-A7 - double data rate multi-port dynamic RAM controller supporting DDR2, DDR3, DDR3L, LPDDR2, LPDDR3 up to 533MHz - peripherals for audio, video processing - 1 gigabit + 1 megabit Ethernet controllers - 6 CAN controllers - trust zone support - DVFS for CPU - criptography IPs Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
61 lines
1.8 KiB
Diff
61 lines
1.8 KiB
Diff
From 372fa27d07f66f97a4bf45621c1b840ce8417a85 Mon Sep 17 00:00:00 2001
|
|
From: Claudiu Beznea <claudiu.beznea@microchip.com>
|
|
Date: Mon, 23 Aug 2021 16:19:15 +0300
|
|
Subject: [PATCH 226/247] ARM: dts: at91: sama7g5: add shdwc node
|
|
|
|
Add shutdown controller node and enable it.
|
|
|
|
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
|
|
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
|
|
Link: https://lore.kernel.org/r/20210823131915.23857-5-claudiu.beznea@microchip.com
|
|
---
|
|
arch/arm/boot/dts/at91-sama7g5ek.dts | 9 +++++++++
|
|
arch/arm/boot/dts/sama7g5.dtsi | 11 +++++++++++
|
|
2 files changed, 20 insertions(+)
|
|
|
|
diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts
|
|
index 4cbed98cc2f4..8b13b031a167 100644
|
|
--- a/arch/arm/boot/dts/at91-sama7g5ek.dts
|
|
+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts
|
|
@@ -634,6 +634,15 @@ &sdmmc2 {
|
|
pinctrl-0 = <&pinctrl_sdmmc2_default>;
|
|
};
|
|
|
|
+&shdwc {
|
|
+ atmel,shdwc-debouncer = <976>;
|
|
+ status = "okay";
|
|
+
|
|
+ input@0 {
|
|
+ reg = <0>;
|
|
+ };
|
|
+};
|
|
+
|
|
&spdifrx {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spdifrx_default>;
|
|
diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
|
|
index 3a4315ac0eb0..e50806cf7660 100644
|
|
--- a/arch/arm/boot/dts/sama7g5.dtsi
|
|
+++ b/arch/arm/boot/dts/sama7g5.dtsi
|
|
@@ -122,6 +122,17 @@ pmc: pmc@e0018000 {
|
|
clock-names = "td_slck", "md_slck", "main_xtal";
|
|
};
|
|
|
|
+ shdwc: shdwc@e001d010 {
|
|
+ compatible = "microchip,sama7g5-shdwc", "syscon";
|
|
+ reg = <0xe001d010 0x10>;
|
|
+ clocks = <&clk32k 0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ atmel,wakeup-rtc-timer;
|
|
+ atmel,wakeup-rtt-timer;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
rtt: rtt@e001d020 {
|
|
compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
|
|
reg = <0xe001d020 0x30>;
|
|
--
|
|
2.32.0
|
|
|