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241 lines
6.9 KiB
Diff
241 lines
6.9 KiB
Diff
From b00b5eafa7e8d059bd0ce844e66f648916953270 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sun, 3 Jan 2016 19:11:22 +0100
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Subject: [PATCH 2/3] phy: ralink-usb: add driver for Mediatek/Ralink
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Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
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The driver is trivial and only sets up power and host mode.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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.../devicetree/bindings/phy/ralink-usb-phy.txt | 17 ++
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drivers/phy/Kconfig | 8 +
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drivers/phy/Makefile | 1 +
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drivers/phy/phy-ralink-usb.c | 171 ++++++++++++++++++++
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4 files changed, 197 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
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create mode 100644 drivers/phy/phy-ralink-usb.c
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
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@@ -0,0 +1,17 @@
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+Mediatek/Ralink USB PHY
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+
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+Required properties:
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+ - compatible: ralink,rt3352-usbphy or mediatek,mt7620-usbphy
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+ - #phy-cells: should be 0
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+ - resets: the two reset controllers for host and device
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+ - reset-names: the names of the 2 reset controllers
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+
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+Example:
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+
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+usbphy: phy {
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+ compatible = "mediatek,mt7620-usbphy";
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+ #phy-cells = <0>;
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+
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+ resets = <&rstctrl 22 &rstctrl 25>;
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+ reset-names = "host", "device";
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+};
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--- a/drivers/phy/Kconfig
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+++ b/drivers/phy/Kconfig
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@@ -331,6 +331,14 @@ config PHY_XGENE
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help
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This option enables support for APM X-Gene SoC multi-purpose PHY.
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+config PHY_RALINK_USB
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+ tristate "Ralink USB PHY driver"
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+ select GENERIC_PHY
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+ depends on RALINK
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+ help
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+ This option enables support for the Ralink USB PHY found inside
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+ RT3352 and MT7620.
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+
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config PHY_STIH407_USB
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tristate "STMicroelectronics USB2 picoPHY driver for STiH407 family"
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depends on RESET_CONTROLLER
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--- a/drivers/phy/Makefile
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+++ b/drivers/phy/Makefile
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@@ -46,3 +46,4 @@ obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-
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obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
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obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o
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obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
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+obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
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--- /dev/null
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+++ b/drivers/phy/phy-ralink-usb.c
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@@ -0,0 +1,175 @@
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+/*
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+ * Allwinner ralink USB phy driver
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+ *
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+ * Copyright (C) 2016 John Crispin <blogic@openwrt.org>
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+ *
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+ * Based on code from
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+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/delay.h>
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+#include <linux/err.h>
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+#include <linux/io.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/mutex.h>
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+#include <linux/phy/phy.h>
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+#include <linux/platform_device.h>
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+#include <linux/reset.h>
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+#include <linux/of_platform.h>
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+
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+#include <asm/mach-ralink/ralink_regs.h>
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+
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+#define RT_SYSC_REG_SYSCFG1 0x014
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+#define RT_SYSC_REG_CLKCFG1 0x030
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+#define RT_SYSC_REG_USB_PHY_CFG 0x05c
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+
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+#define RT_RSTCTRL_UDEV BIT(25)
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+#define RT_RSTCTRL_UHST BIT(22)
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+#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
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+
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+#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
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+#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
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+#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
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+#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
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+
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+#define USB_PHY_UTMI_8B60M BIT(1)
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+#define UDEV_WAKEUP BIT(0)
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+
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+struct ralink_usb_phy {
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+ struct reset_control *rstdev;
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+ struct reset_control *rsthost;
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+ u32 clk;
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+ struct phy *phy;
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+};
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+
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+static int ralink_usb_phy_power_on(struct phy *_phy)
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+{
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+ struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
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+ u32 t;
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+
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+ /* enable the phy */
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+ rt_sysc_m32(0, phy->clk, RT_SYSC_REG_CLKCFG1);
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+
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+ /* setup host mode */
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+ rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
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+
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+ /* deassert the reset lines */
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+ reset_control_deassert(phy->rsthost);
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+ reset_control_deassert(phy->rstdev);
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+
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+ /*
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+ * The SDK kernel had a delay of 100ms. however on device
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+ * testing showed that 10ms is enough
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+ */
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+ mdelay(10);
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+
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+ /* print some status info */
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+ t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
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+ dev_info(&phy->phy->dev, "remote usb device wakeup %s\n",
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+ (t & UDEV_WAKEUP) ? ("enabled") : ("disabled"));
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+ if (t & USB_PHY_UTMI_8B60M)
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+ dev_info(&phy->phy->dev, "UTMI 8bit 60MHz\n");
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+ else
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+ dev_info(&phy->phy->dev, "UTMI 16bit 30MHz\n");
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+
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+ return 0;
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+}
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+
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+static int ralink_usb_phy_power_off(struct phy *_phy)
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+{
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+ struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
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+
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+ /* disable the phy */
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+ rt_sysc_m32(phy->clk, 0, RT_SYSC_REG_CLKCFG1);
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+
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+ /* assert the reset lines */
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+ reset_control_assert(phy->rstdev);
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+ reset_control_assert(phy->rsthost);
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+
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+ return 0;
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+}
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+
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+static struct phy_ops ralink_usb_phy_ops = {
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+ .power_on = ralink_usb_phy_power_on,
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+ .power_off = ralink_usb_phy_power_off,
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+ .owner = THIS_MODULE,
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+};
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+
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+static const struct of_device_id ralink_usb_phy_of_match[] = {
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+ {
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+ .compatible = "ralink,rt3352-usbphy",
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+ .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN |
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+ RT_CLKCFG1_UPHY0_CLK_EN)
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+ },
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+ {
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+ .compatible = "mediatek,mt7620-usbphy",
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+ .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN |
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+ MT7620_CLKCFG1_UPHY0_CLK_EN) },
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+ { },
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+};
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+MODULE_DEVICE_TABLE(of, ralink_usb_phy_of_match);
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+
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+static int ralink_usb_phy_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct phy_provider *phy_provider;
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+ const struct of_device_id *match;
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+ struct ralink_usb_phy *phy;
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+
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+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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+ if (!phy)
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+ return -ENOMEM;
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+
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+ match = of_match_device(ralink_usb_phy_of_match, &pdev->dev);
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+ if (!match)
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+ return -ENODEV;
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+
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+ phy->clk = (int) match->data;
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+
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+ phy->rsthost = devm_reset_control_get(&pdev->dev, "host");
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+ if (IS_ERR(phy->rsthost)) {
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+ dev_err(dev, "host reset is missing\n");
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+ return PTR_ERR(phy->rsthost);
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+ }
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+
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+ phy->rstdev = devm_reset_control_get(&pdev->dev, "device");
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+ if (IS_ERR(phy->rstdev)) {
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+ dev_err(dev, "device reset is missing\n");
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+ return PTR_ERR(phy->rstdev);
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+ }
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+
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+ phy->phy = devm_phy_create(dev, NULL, &ralink_usb_phy_ops);
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+ if (IS_ERR(phy->phy)) {
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+ dev_err(dev, "failed to create PHY\n");
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+ return PTR_ERR(phy->phy);
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+ }
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+ phy_set_drvdata(phy->phy, phy);
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+
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+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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+
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+ return PTR_ERR_OR_ZERO(phy_provider);
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+}
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+
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+static struct platform_driver ralink_usb_phy_driver = {
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+ .probe = ralink_usb_phy_probe,
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+ .driver = {
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+ .of_match_table = ralink_usb_phy_of_match,
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+ .name = "ralink-usb-phy",
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+ }
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+};
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+module_platform_driver(ralink_usb_phy_driver);
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+
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+MODULE_DESCRIPTION("Ralink USB phy driver");
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+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
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+MODULE_LICENSE("GPL v2");
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