mirror of
https://github.com/openwrt/openwrt.git
synced 2025-01-01 11:36:49 +00:00
78858e5d6c
In the past few years, we have received several reports about SPI
Flash not working properly. This is caused by excessively fast
clock frequency. It's really annoying to fix them one by one. Let's
reduce these aggressive frequencies to 50 MHz. This is a safe and
suggested value in the vendor SDK.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
(cherry picked from commit 73eeac49be)
Link: https://github.com/openwrt/openwrt/pull/15919
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
182 lines
2.7 KiB
Plaintext
182 lines
2.7 KiB
Plaintext
#include "mt7620a.dtsi"
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/input/input.h>
|
|
|
|
/ {
|
|
compatible = "xiaomi,miwifi-mini", "ralink,mt7620a-soc";
|
|
model = "Xiaomi MiWiFi Mini";
|
|
|
|
aliases {
|
|
led-boot = &led_yellow;
|
|
led-failsafe = &led_red;
|
|
led-running = &led_blue;
|
|
led-upgrade = &led_blue;
|
|
label-mac-device = ðernet;
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "console=ttyS0,115200";
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
led_blue: blue {
|
|
label = "blue:status";
|
|
gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
led_yellow: yellow {
|
|
label = "yellow:status";
|
|
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
led_red: red {
|
|
label = "red:status";
|
|
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
wan {
|
|
label = "green:wan";
|
|
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
lan1 {
|
|
label = "green:lan1";
|
|
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
lan2 {
|
|
label = "green:lan2";
|
|
gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|
|
|
|
keys {
|
|
compatible = "gpio-keys";
|
|
|
|
reset {
|
|
label = "reset";
|
|
gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
|
|
linux,code = <KEY_RESTART>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&gpio1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&spi0 {
|
|
status = "okay";
|
|
|
|
flash@0 {
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <50000000>;
|
|
m25p,fast-read;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "u-boot";
|
|
reg = <0x0 0x30000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@30000 {
|
|
label = "u-boot-env";
|
|
reg = <0x30000 0x10000>;
|
|
};
|
|
|
|
factory: partition@40000 {
|
|
label = "factory";
|
|
reg = <0x40000 0x10000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@50000 {
|
|
compatible = "denx,uimage";
|
|
label = "firmware";
|
|
reg = <0x50000 0xf80000>;
|
|
};
|
|
|
|
partition@fd0000 {
|
|
label = "crash";
|
|
reg = <0xfd0000 0x10000>;
|
|
};
|
|
|
|
partition@fe0000 {
|
|
label = "reserved";
|
|
reg = <0xfe0000 0x10000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@ff0000 {
|
|
label = "Bdata";
|
|
reg = <0xff0000 0x10000>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&ehci {
|
|
status = "okay";
|
|
};
|
|
|
|
&ohci {
|
|
status = "okay";
|
|
};
|
|
|
|
ðernet {
|
|
nvmem-cells = <&macaddr_factory_28>;
|
|
nvmem-cell-names = "mac-address";
|
|
|
|
mediatek,portmap = "llllw";
|
|
};
|
|
|
|
&wmac {
|
|
ralink,mtd-eeprom = <&factory 0x0>;
|
|
|
|
pinctrl-names = "default", "pa_gpio";
|
|
pinctrl-0 = <&pa_pins>;
|
|
pinctrl-1 = <&pa_gpio_pins>;
|
|
};
|
|
|
|
&pcie {
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie0 {
|
|
mt76@0,0 {
|
|
reg = <0x0000 0 0 0 0>;
|
|
mediatek,mtd-eeprom = <&factory 0x8000>;
|
|
ieee80211-freq-limit = <5000000 6000000>;
|
|
};
|
|
};
|
|
|
|
&state_default {
|
|
gpio {
|
|
groups = "ephy", "i2c", "rgmii1";
|
|
function = "gpio";
|
|
};
|
|
};
|
|
|
|
&factory {
|
|
compatible = "nvmem-cells";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
macaddr_factory_28: macaddr@28 {
|
|
reg = <0x28 0x6>;
|
|
};
|
|
};
|