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99545b4bb1
This target adds support for the Allwinner D1 RISC-V based SoCs.
- RISC-V single-core T-Head C906 (RV64GCV)
- Tensilica HiFi4 DSP
- DDR2/DDR3 support
- 10/100/1000M ethernet
- usual peripherals like USB2, SPI, I2C, PWM, etc.
Four boards are supported:
- Dongshan Nezha STU
- 512Mb RAM
- ethernet
- LicheePi RV Dock
- 512Mb RAM
- wireless-only (RTL8723DS)
- MangoPi MQ-Pro
- 512Mb RAM
- there are pads available for an SPI flash
- wireless-only (RTL8723DS)
- Nezha D1
- 512Mb/1Gb/2Gb RAM
- 256Mb NAND flash
- ethernet, wireless
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
51 lines
1.7 KiB
Diff
51 lines
1.7 KiB
Diff
From b300b013de16109f833782d9f4e7ee8cc204780f Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sat, 17 Jul 2021 11:19:29 -0500
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Subject: [PATCH 077/117] spi: spi-sun6i: Dual/Quad RX Support
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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drivers/spi/spi-sun6i.c | 17 +++++++++++++++--
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1 file changed, 15 insertions(+), 2 deletions(-)
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--- a/drivers/spi/spi-sun6i.c
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+++ b/drivers/spi/spi-sun6i.c
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@@ -82,6 +82,8 @@
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#define SUN6I_XMIT_CNT_REG 0x34
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#define SUN6I_BURST_CTL_CNT_REG 0x38
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+#define SUN6I_BURST_CTL_CNT_QUAD_EN BIT(29)
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+#define SUN6I_BURST_CTL_CNT_DUAL_EN BIT(28)
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#define SUN6I_TXDATA_REG 0x200
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#define SUN6I_RXDATA_REG 0x300
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@@ -415,7 +417,17 @@ static int sun6i_spi_transfer_one(struct
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/* Setup the counters */
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sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
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sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
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- sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len);
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+
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+ reg = tx_len;
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+ switch (tfr->rx_nbits) {
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+ case SPI_NBITS_QUAD:
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+ reg |= SUN6I_BURST_CTL_CNT_QUAD_EN;
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+ break;
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+ case SPI_NBITS_DUAL:
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+ reg |= SUN6I_BURST_CTL_CNT_DUAL_EN;
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+ break;
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+ }
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+ sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, reg);
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if (!use_dma) {
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/* Fill the TX FIFO */
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@@ -632,7 +644,8 @@ static int sun6i_spi_probe(struct platfo
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master->set_cs = sun6i_spi_set_cs;
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master->transfer_one = sun6i_spi_transfer_one;
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master->num_chipselect = 4;
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- master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
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+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST
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+ | SPI_RX_DUAL | SPI_RX_QUAD;
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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master->dev.of_node = pdev->dev.of_node;
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master->auto_runtime_pm = true;
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