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0a63e72fbb
Zbtlink ZBT-WG1608 is a Wi-Fi router intendent to use with WWAN (4G/5G)
modems.
Specifications:
* SoC: MediaTek MT7621A
* RAM: 256/512 MiB
* Flash: 16/32 MiB (SPI NOR)
* Wi-Fi:
* MediaTek MT7603E : 2.4Ghz
* MediaTek MT7613BE : 5Ghz
* Ethernet: 10/100/1000 Mbps Ethernet x5 ports (4xLAN + WAN)
* M.2: 1x slot with USB&SIM
* EM7455/EM12-G/EM160R/RM500Q-AE
* USB: 1x 3.0 Type-A port
* External storage: 1x microSD (SDXC) slot
* UART: console (115200 baud)
* LED:
* 1 power indicator
* 1 WLAN 2.4G controlled (wlan 2G)
* 3 SoC controlled (wlan 5G, wwan, internet)
* 5 per Eth phy (4xLAN + WAN)
MAC Addresses:
* LAN : f8:5e:3c:xx:xx:e0 (Factory, 0xe000 (hex))
* WAN : f8:5e:3c:xx:xx:e1 (Factory, 0xe006 (hex))
* 2.4 GHz: f8:5e:3c:xx:xx:de (Factory, 0x0004 (hex))
* 5 GHz : f8:5e:3c:xx:xx:df (Factory, 0x8004 (hex))
Installation:
* Vendor's firmware is OpenWrt (LEDE) based, so the sysupgrade image can
be directly used to install OpenWrt. Firmware must be upgraded using the
'force' and 'do not save configuration' command line options (or
correspondig web interface checkboxes) since the vendor firmware is from
the pre-DSA era.
Recovery Mode:
* Press reset button, power up the device, wait for about 10sec.
* Upload sysupgrade image through the firmware recovery mode web page at
192.168.1.1.
Signed-off-by: Kim DoHyoung <azusahmr@k-on.kr>
(cherry picked from commit 0bbd5699c8
)
200 lines
3.0 KiB
Plaintext
200 lines
3.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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/ {
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compatible = "zbtlink,zbt-wg1608", "mediatek,mt7621-soc";
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aliases {
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led-boot = &led_internet;
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led-failsafe = &led_internet;
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led-running = &led_internet;
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led-upgrade = &led_internet;
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label-mac-device = &gmac0;
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};
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_internet: internet {
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label = "green:internet";
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gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
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};
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wwan {
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label = "green:wwan";
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gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "usbport";
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trigger-sources = <&hub_port2>;
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};
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wifi5g {
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label = "green:wifi5g";
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gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy1tpt";
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};
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};
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};
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&sdhci {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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flash0: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <50000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_factory_e000: macaddr@e000 {
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reg = <0xe000 0x6>;
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};
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macaddr_factory_e006: macaddr@e006 {
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reg = <0xe006 0x6>;
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};
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};
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firmware: partition@50000 {
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compatible = "denx,uimage";
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label = "firmware";
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};
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};
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};
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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wifi@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x0000>;
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};
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};
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&pcie1 {
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wifi@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x8000>;
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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&gmac0 {
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nvmem-cells = <&macaddr_factory_e000>;
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nvmem-cell-names = "mac-address";
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};
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&gmac1 {
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status = "okay";
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label = "wan";
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phy-handle = <ðphy4>;
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nvmem-cells = <&macaddr_factory_e006>;
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nvmem-cell-names = "mac-address";
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};
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&mdio {
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ethphy4: ethernet-phy@4 {
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reg = <4>;
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};
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};
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&switch0 {
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ports {
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port@0 {
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status = "okay";
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label = "lan1";
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};
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port@1 {
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status = "okay";
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label = "lan2";
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};
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port@2 {
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status = "okay";
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label = "lan3";
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};
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port@3 {
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status = "okay";
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label = "lan4";
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};
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};
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};
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&state_default {
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gpio {
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groups = "wdt", "uart2", "jtag";
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function = "gpio";
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};
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};
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&xhci_ehci_port1 {
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#address-cells = <1>;
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#size-cells = <0>;
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hub_port2: port@2 {
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reg = <2>;
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#trigger-source-cells = <0>;
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};
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port@4 {
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reg = <4>;
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#trigger-source-cells = <0>;
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};
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};
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