mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 23:42:43 +00:00
659f4a13dd
With Linux 6.1 many of our downstream patches and out-of-tree files can be removed or at least replaced by backported upstream commits. Signed-off-by: Daniel Golle <daniel@makrotopia.org> [fix CMDLINE_OVERRIDE for arm64] Signed-off-by: Bjørn Mork <bjorn@mork.no>
104 lines
4.0 KiB
Diff
104 lines
4.0 KiB
Diff
From 5d911479e4c732729bfa798e4a9e3e5aec3e30a7 Mon Sep 17 00:00:00 2001
|
|
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
|
Date: Fri, 20 Jan 2023 10:20:36 +0100
|
|
Subject: [PATCH 04/15] clk: mediatek: clk-mux: Propagate struct device for
|
|
mtk-mux
|
|
|
|
Like done for other clocks, propagate struct device for mtk mux clocks
|
|
registered through clk-mux helpers to enable runtime pm support.
|
|
|
|
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
|
Tested-by: Miles Chen <miles.chen@mediatek.com>
|
|
Link: https://lore.kernel.org/r/20230120092053.182923-7-angelogioacchino.delregno@collabora.com
|
|
Tested-by: Mingming Su <mingming.su@mediatek.com>
|
|
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
|
|
[daniel@makrotopia.org: removed parts not relevant for OpenWrt]
|
|
---
|
|
drivers/clk/mediatek/clk-mt7986-infracfg.c | 3 ++-
|
|
drivers/clk/mediatek/clk-mt7986-topckgen.c | 3 ++-
|
|
drivers/clk/mediatek/clk-mux.c | 14 ++++++++------
|
|
drivers/clk/mediatek/clk-mux.h | 3 ++-
|
|
4 files changed, 14 insertions(+), 9 deletions(-)
|
|
|
|
--- a/drivers/clk/mediatek/clk-mt7986-infracfg.c
|
|
+++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c
|
|
@@ -178,7 +178,8 @@ static int clk_mt7986_infracfg_probe(str
|
|
return -ENOMEM;
|
|
|
|
mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
|
|
- mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
|
|
+ mtk_clk_register_muxes(&pdev->dev, infra_muxes,
|
|
+ ARRAY_SIZE(infra_muxes), node,
|
|
&mt7986_clk_lock, clk_data);
|
|
mtk_clk_register_gates(&pdev->dev, node, infra_clks,
|
|
ARRAY_SIZE(infra_clks), clk_data);
|
|
--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
|
|
+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
|
|
@@ -303,7 +303,8 @@ static int clk_mt7986_topckgen_probe(str
|
|
mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
|
|
clk_data);
|
|
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
|
|
- mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
|
|
+ mtk_clk_register_muxes(&pdev->dev, top_muxes,
|
|
+ ARRAY_SIZE(top_muxes), node,
|
|
&mt7986_clk_lock, clk_data);
|
|
|
|
clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
|
|
--- a/drivers/clk/mediatek/clk-mux.c
|
|
+++ b/drivers/clk/mediatek/clk-mux.c
|
|
@@ -154,9 +154,10 @@ const struct clk_ops mtk_mux_gate_clr_se
|
|
};
|
|
EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
|
|
|
|
-static struct clk_hw *mtk_clk_register_mux(const struct mtk_mux *mux,
|
|
- struct regmap *regmap,
|
|
- spinlock_t *lock)
|
|
+static struct clk_hw *mtk_clk_register_mux(struct device *dev,
|
|
+ const struct mtk_mux *mux,
|
|
+ struct regmap *regmap,
|
|
+ spinlock_t *lock)
|
|
{
|
|
struct mtk_clk_mux *clk_mux;
|
|
struct clk_init_data init = {};
|
|
@@ -177,7 +178,7 @@ static struct clk_hw *mtk_clk_register_m
|
|
clk_mux->lock = lock;
|
|
clk_mux->hw.init = &init;
|
|
|
|
- ret = clk_hw_register(NULL, &clk_mux->hw);
|
|
+ ret = clk_hw_register(dev, &clk_mux->hw);
|
|
if (ret) {
|
|
kfree(clk_mux);
|
|
return ERR_PTR(ret);
|
|
@@ -198,7 +199,8 @@ static void mtk_clk_unregister_mux(struc
|
|
kfree(mux);
|
|
}
|
|
|
|
-int mtk_clk_register_muxes(const struct mtk_mux *muxes,
|
|
+int mtk_clk_register_muxes(struct device *dev,
|
|
+ const struct mtk_mux *muxes,
|
|
int num, struct device_node *node,
|
|
spinlock_t *lock,
|
|
struct clk_hw_onecell_data *clk_data)
|
|
@@ -222,7 +224,7 @@ int mtk_clk_register_muxes(const struct
|
|
continue;
|
|
}
|
|
|
|
- hw = mtk_clk_register_mux(mux, regmap, lock);
|
|
+ hw = mtk_clk_register_mux(dev, mux, regmap, lock);
|
|
|
|
if (IS_ERR(hw)) {
|
|
pr_err("Failed to register clk %s: %pe\n", mux->name,
|
|
--- a/drivers/clk/mediatek/clk-mux.h
|
|
+++ b/drivers/clk/mediatek/clk-mux.h
|
|
@@ -83,7 +83,8 @@ extern const struct clk_ops mtk_mux_gate
|
|
0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \
|
|
mtk_mux_clr_set_upd_ops)
|
|
|
|
-int mtk_clk_register_muxes(const struct mtk_mux *muxes,
|
|
+int mtk_clk_register_muxes(struct device *dev,
|
|
+ const struct mtk_mux *muxes,
|
|
int num, struct device_node *node,
|
|
spinlock_t *lock,
|
|
struct clk_hw_onecell_data *clk_data);
|