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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
130 lines
4.3 KiB
Diff
130 lines
4.3 KiB
Diff
From f778553f296792f4d1e8b3552603ad6116ea3eb3 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Thu, 3 Nov 2022 14:49:44 +0100
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Subject: [PATCH] clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple
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conf
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Rework nss_port5/6 to use the new multiple configuration implementation
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and correctly fix the clocks for these port under some corner case.
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This is particularly relevant for device that have 2.5G or 10G port
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connected to port5 or port 6 on ipq8074. As the parent are shared
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across multiple port it may be required to select the correct
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configuration to accomplish the desired clock. Without this patch such
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port doesn't work in some specific ethernet speed as the clock will be
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set to the wrong frequency as we just select the first configuration for
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the related frequency instead of selecting the best one.
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Tested-by: Robert Marko <robimarko@gmail.com> # ipq8074 Qnap QHora-301W
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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drivers/clk/qcom/gcc-ipq8074.c | 64 +++++++++++++++++++++++++---------
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1 file changed, 48 insertions(+), 16 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -1682,13 +1682,21 @@ static struct clk_regmap_div nss_port4_t
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},
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};
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+static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
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+ C(P_UNIPHY1_RX, 12.5, 0, 0),
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+ C(P_UNIPHY0_RX, 5, 0, 0),
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+};
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+
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+static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
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+ C(P_UNIPHY1_RX, 2.5, 0, 0),
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+ C(P_UNIPHY0_RX, 1, 0, 0),
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+};
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+
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static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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- F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
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- F(25000000, P_UNIPHY0_RX, 5, 0, 0),
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+ FM(25000000, ftbl_nss_port5_rx_clk_src_25),
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F(78125000, P_UNIPHY1_RX, 4, 0, 0),
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- F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
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- F(125000000, P_UNIPHY0_RX, 1, 0, 0),
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+ FM(125000000, ftbl_nss_port5_rx_clk_src_125),
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F(156250000, P_UNIPHY1_RX, 2, 0, 0),
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F(312500000, P_UNIPHY1_RX, 1, 0, 0),
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{ }
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@@ -1744,13 +1752,21 @@ static struct clk_regmap_div nss_port5_r
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},
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};
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+static struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
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+ C(P_UNIPHY1_TX, 12.5, 0, 0),
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+ C(P_UNIPHY0_TX, 5, 0, 0),
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+};
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+
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+static struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
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+ C(P_UNIPHY1_TX, 2.5, 0, 0),
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+ C(P_UNIPHY0_TX, 1, 0, 0),
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+};
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+
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static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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- F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
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- F(25000000, P_UNIPHY0_TX, 5, 0, 0),
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+ FM(25000000, ftbl_nss_port5_tx_clk_src_25),
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F(78125000, P_UNIPHY1_TX, 4, 0, 0),
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- F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
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- F(125000000, P_UNIPHY0_TX, 1, 0, 0),
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+ FM(125000000, ftbl_nss_port5_tx_clk_src_125),
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F(156250000, P_UNIPHY1_TX, 2, 0, 0),
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F(312500000, P_UNIPHY1_TX, 1, 0, 0),
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{ }
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@@ -1806,13 +1822,21 @@ static struct clk_regmap_div nss_port5_t
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},
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};
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+static struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = {
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+ C(P_UNIPHY2_RX, 5, 0, 0),
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+ C(P_UNIPHY2_RX, 12.5, 0, 0),
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+};
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+
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+static struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = {
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+ C(P_UNIPHY2_RX, 1, 0, 0),
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+ C(P_UNIPHY2_RX, 2.5, 0, 0),
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+};
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+
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static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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- F(25000000, P_UNIPHY2_RX, 5, 0, 0),
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- F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
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+ FM(25000000, ftbl_nss_port6_rx_clk_src_25),
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F(78125000, P_UNIPHY2_RX, 4, 0, 0),
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- F(125000000, P_UNIPHY2_RX, 1, 0, 0),
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- F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
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+ FM(125000000, ftbl_nss_port6_rx_clk_src_125),
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F(156250000, P_UNIPHY2_RX, 2, 0, 0),
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F(312500000, P_UNIPHY2_RX, 1, 0, 0),
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{ }
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@@ -1863,13 +1887,21 @@ static struct clk_regmap_div nss_port6_r
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},
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};
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+static struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = {
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+ C(P_UNIPHY2_TX, 5, 0, 0),
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+ C(P_UNIPHY2_TX, 12.5, 0, 0),
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+};
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+
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+static struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = {
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+ C(P_UNIPHY2_TX, 1, 0, 0),
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+ C(P_UNIPHY2_TX, 2.5, 0, 0),
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+};
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+
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static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
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F(19200000, P_XO, 1, 0, 0),
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- F(25000000, P_UNIPHY2_TX, 5, 0, 0),
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- F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
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+ FM(25000000, ftbl_nss_port6_tx_clk_src_25),
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F(78125000, P_UNIPHY2_TX, 4, 0, 0),
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- F(125000000, P_UNIPHY2_TX, 1, 0, 0),
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- F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
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+ FM(125000000, ftbl_nss_port6_tx_clk_src_125),
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F(156250000, P_UNIPHY2_TX, 2, 0, 0),
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F(312500000, P_UNIPHY2_TX, 1, 0, 0),
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{ }
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