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Currently, ipq807x only covers Qualcomm IPQ807x SoC-s. However, Qualcomm also has IPQ60xx and IPQ50xx SoC-s under the AX WiSoC-s and they share a lot of stuff with IPQ807x, especially IPQ60xx so to avoid duplicating kernel patches and everything lets make a common target with per SoC subtargets. Start doing that by renaming ipq807x to qualcommax so that dependencies on ipq807x target can be updated. Signed-off-by: Robert Marko <robimarko@gmail.com>
44 lines
1.5 KiB
Diff
44 lines
1.5 KiB
Diff
From fb1f6850be00d8dd8a54017be4c1336e224069ac Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Wed, 16 Nov 2022 22:26:25 +0100
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Subject: [PATCH] arm64: dts: qcom: ipq8074: use msi-parent for PCIe
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Instead of hardcoding the IRQ, simply use msi-parent instead.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 +++-----
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1 file changed, 3 insertions(+), 5 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -699,7 +699,7 @@
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reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
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ranges = <0 0xb00a000 0xffd>;
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- v2m@0 {
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+ gic_v2m0: v2m@0 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0xffd>;
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@@ -811,8 +811,7 @@
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ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
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<0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
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- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-names = "msi";
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+ msi-parent = <&gic_v2m0>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 142
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@@ -873,8 +872,7 @@
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ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
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<0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
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- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-names = "msi";
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+ msi-parent = <&gic_v2m0>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 75
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