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3ea6125c50
Currently, the MT7530 DSA subdriver configures the MT7530 switch to provide
direct access to switch PHYs, meaning, the switch PHYs listen on the MDIO
bus the switch listens on. The PHY muxing feature makes use of this.
This is problematic as the PHY may be attached before the switch is
initialised, in which case, the PHY will fail to be attached.
Since commit 91374ba537bd ("net: dsa: mt7530: support OF-based registration
of switch MDIO bus") on mainline Linux, we can describe the switch PHYs on
the MDIO bus of the switch on the device tree.
When the PHY is described this way, the switch will be initialised first,
then the switch MDIO bus will be registered. Only after these steps, the
PHY will be attached.
Describe the switch PHYs on mt7621.dtsi and remove defining the switch PHY
on the SoC's mdio bus node. When the PHY muxing is in use, the interrupts
for the muxed PHY won't work, therefore delete the "interrupts" property on
the devices where the PHY muxing feature is in use.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
203 lines
3.1 KiB
Plaintext
203 lines
3.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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/ {
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aliases {
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led-boot = &led_power;
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led-failsafe = &led_power;
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led-running = &led_power;
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led-upgrade = &led_power;
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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wps {
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label = "wps";
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gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_power: power {
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function = LED_FUNCTION_POWER;
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color = <LED_COLOR_ID_BLUE>;
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gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
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};
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wlan5g {
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label = "blue:wlan5g";
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gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy1tpt";
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};
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wlan2g {
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label = "blue:wlan2g";
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gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy0tpt";
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};
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};
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};
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&i2c {
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status = "okay";
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};
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&sdhci {
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status = "okay";
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};
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&nand {
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status = "okay";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0xe0000>;
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read-only;
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};
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partition@e0000 {
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label = "u-boot-env";
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reg = <0xe0000 0x100000>;
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read-only;
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};
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partition@1e0000 {
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label = "factory";
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reg = <0x1e0000 0x100000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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eeprom_factory_0: eeprom@0 {
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reg = <0x0 0x4da8>;
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};
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eeprom_factory_8000: eeprom@8000 {
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reg = <0x8000 0x4da8>;
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};
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macaddr_factory_e000: macaddr@e000 {
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reg = <0xe000 0x6>;
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};
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};
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};
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partition@2e0000 {
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label = "factory2";
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reg = <0x2e0000 0x100000>;
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read-only;
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};
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partition@3e0000 {
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label = "kernel";
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reg = <0x3e0000 0x400000>;
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};
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partition@7e0000 {
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label = "ubi";
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reg = <0x7e0000 0x2e00000>;
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};
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partition@35e0000 {
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label = "firmware2";
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reg = <0x35e0000 0x3200000>;
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};
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};
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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wifi0: wifi@0,0 {
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compatible = "pci14c3,7615";
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reg = <0x0000 0 0 0 0>;
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nvmem-cells = <&eeprom_factory_0>;
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nvmem-cell-names = "eeprom";
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ieee80211-freq-limit = <2400000 2500000>;
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};
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};
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&pcie1 {
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wifi1: wifi@0,0 {
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compatible = "pci14c3,7615";
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reg = <0x0000 0 0 0 0>;
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nvmem-cells = <&eeprom_factory_8000>;
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nvmem-cell-names = "eeprom";
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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&gmac0 {
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nvmem-cells = <&macaddr_factory_e000>;
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nvmem-cell-names = "mac-address";
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};
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&gmac1 {
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status = "okay";
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label = "wan";
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phy-handle = <ðphy0>;
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nvmem-cells = <&macaddr_factory_e000>;
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nvmem-cell-names = "mac-address";
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};
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ðphy0 {
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/delete-property/ interrupts;
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};
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&switch0 {
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ports {
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port@1 {
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status = "okay";
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label = "lan1";
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};
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port@2 {
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status = "okay";
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label = "lan2";
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};
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port@3 {
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status = "okay";
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label = "lan3";
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};
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port@4 {
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status = "okay";
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label = "lan4";
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};
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};
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};
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&state_default {
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gpio {
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groups = "uart2", "uart3", "i2c";
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function = "gpio";
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};
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};
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