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99545b4bb1
This target adds support for the Allwinner D1 RISC-V based SoCs.
- RISC-V single-core T-Head C906 (RV64GCV)
- Tensilica HiFi4 DSP
- DDR2/DDR3 support
- 10/100/1000M ethernet
- usual peripherals like USB2, SPI, I2C, PWM, etc.
Four boards are supported:
- Dongshan Nezha STU
- 512Mb RAM
- ethernet
- LicheePi RV Dock
- 512Mb RAM
- wireless-only (RTL8723DS)
- MangoPi MQ-Pro
- 512Mb RAM
- there are pads available for an SPI flash
- wireless-only (RTL8723DS)
- Nezha D1
- 512Mb/1Gb/2Gb RAM
- 256Mb NAND flash
- ethernet, wireless
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
147 lines
4.9 KiB
Diff
147 lines
4.9 KiB
Diff
From ec8dfb455da3822451129257ab21e2f0d03a6ae3 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Fri, 16 Jul 2021 21:46:31 -0500
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Subject: [PATCH 076/117] spi: spi-sun6i: Add Allwinner R329 support
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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drivers/spi/spi-sun6i.c | 78 ++++++++++++++++++++++++++---------------
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1 file changed, 49 insertions(+), 29 deletions(-)
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--- a/drivers/spi/spi-sun6i.c
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+++ b/drivers/spi/spi-sun6i.c
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@@ -30,6 +30,7 @@
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#define SUN6I_GBL_CTL_REG 0x04
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#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
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#define SUN6I_GBL_CTL_MASTER BIT(1)
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+#define SUN6I_GBL_CTL_SAMPLE_MODE BIT(2)
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#define SUN6I_GBL_CTL_TP BIT(7)
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#define SUN6I_GBL_CTL_RST BIT(31)
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@@ -87,6 +88,8 @@
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struct sun6i_spi_quirks {
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unsigned long fifo_depth;
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+ bool has_divider : 1;
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+ bool has_new_sample_mode : 1;
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};
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struct sun6i_spi {
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@@ -362,38 +365,44 @@ static int sun6i_spi_transfer_one(struct
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sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
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/* Ensure that we have a parent clock fast enough */
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- mclk_rate = clk_get_rate(sspi->mclk);
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- if (mclk_rate < (2 * tfr->speed_hz)) {
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- clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
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+ if (sspi->quirks->has_divider) {
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mclk_rate = clk_get_rate(sspi->mclk);
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- }
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+ if (mclk_rate < (2 * tfr->speed_hz)) {
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+ clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
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+ mclk_rate = clk_get_rate(sspi->mclk);
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+ }
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- /*
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- * Setup clock divider.
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- *
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- * We have two choices there. Either we can use the clock
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- * divide rate 1, which is calculated thanks to this formula:
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- * SPI_CLK = MOD_CLK / (2 ^ cdr)
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- * Or we can use CDR2, which is calculated with the formula:
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- * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
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- * Wether we use the former or the latter is set through the
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- * DRS bit.
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- *
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- * First try CDR2, and if we can't reach the expected
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- * frequency, fall back to CDR1.
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- */
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- div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
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- div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
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- if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
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- reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
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- tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
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+ /*
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+ * Setup clock divider.
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+ *
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+ * We have two choices there. Either we can use the clock
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+ * divide rate 1, which is calculated thanks to this formula:
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+ * SPI_CLK = MOD_CLK / (2 ^ cdr)
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+ * Or we can use CDR2, which is calculated with the formula:
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+ * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
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+ * Wether we use the former or the latter is set through the
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+ * DRS bit.
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+ *
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+ * First try CDR2, and if we can't reach the expected
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+ * frequency, fall back to CDR1.
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+ */
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+ div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
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+ div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
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+ if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
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+ reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
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+ tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
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+ } else {
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+ div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
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+ reg = SUN6I_CLK_CTL_CDR1(div);
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+ tfr->effective_speed_hz = mclk_rate / (1 << div);
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+ }
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+ sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
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} else {
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- div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
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- reg = SUN6I_CLK_CTL_CDR1(div);
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- tfr->effective_speed_hz = mclk_rate / (1 << div);
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+ clk_set_rate(sspi->mclk, tfr->speed_hz);
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+ mclk_rate = clk_get_rate(sspi->mclk);
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+ tfr->effective_speed_hz = mclk_rate;
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}
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- sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
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/* Finally enable the bus - doing so before might raise SCK to HIGH */
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reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG);
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reg |= SUN6I_GBL_CTL_BUS_ENABLE;
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@@ -518,6 +527,7 @@ static int sun6i_spi_runtime_resume(stru
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struct spi_master *master = dev_get_drvdata(dev);
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struct sun6i_spi *sspi = spi_master_get_devdata(master);
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int ret;
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+ u32 reg;
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ret = clk_prepare_enable(sspi->hclk);
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if (ret) {
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@@ -537,8 +547,10 @@ static int sun6i_spi_runtime_resume(stru
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goto err2;
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}
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- sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
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- SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
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+ reg = SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP;
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+ if (sspi->quirks->has_new_sample_mode)
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+ reg |= SUN6I_GBL_CTL_SAMPLE_MODE;
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+ sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
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return 0;
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@@ -729,15 +741,23 @@ static int sun6i_spi_remove(struct platf
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static const struct sun6i_spi_quirks sun6i_a31_spi_quirks = {
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.fifo_depth = SUN6I_FIFO_DEPTH,
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+ .has_divider = true,
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};
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static const struct sun6i_spi_quirks sun8i_h3_spi_quirks = {
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.fifo_depth = SUN8I_FIFO_DEPTH,
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+ .has_divider = true,
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+};
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+
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+static const struct sun6i_spi_quirks sun50i_r329_spi_quirks = {
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+ .fifo_depth = SUN8I_FIFO_DEPTH,
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+ .has_new_sample_mode = true,
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};
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static const struct of_device_id sun6i_spi_match[] = {
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{ .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_quirks },
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{ .compatible = "allwinner,sun8i-h3-spi", .data = &sun8i_h3_spi_quirks },
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+ { .compatible = "allwinner,sun50i-r329-spi", .data = &sun50i_r329_spi_quirks },
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{}
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};
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MODULE_DEVICE_TABLE(of, sun6i_spi_match);
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