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https://github.com/openwrt/openwrt.git
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b4c02c9998
Removed upstreamed patches:
generic/pending-5.4
445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch
446-mtd-spinand-gigadevice-Add-QE-Bit.patch
pistachio/patches-5.4
150-pwm-img-Fix-null-pointer-access-in-probe.patch
Manually rebased:
layerscape/patches-5.4
801-audio-0011-Revert-ASoC-fsl_sai-add-of_match-data.patch
801-audio-0039-MLK-16224-6-ASoC-fsl_sai-fix-DSD-suspend-resume.patch
801-audio-0073-MLK-21957-3-ASoC-fsl_sai-add-bitcount-and-timestamp-.patch
820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh.patch
All modifications made by update_kernel.sh
Build system: x86_64
Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711,
mvebu (mamba, rango), x86_64, ramips/mt7621
Run-tested: ipq806x/R7800, mvebu (mamba, rango), x86_64, ramips (RT-AC57U)
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
[alter 820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
102 lines
3.5 KiB
Diff
102 lines
3.5 KiB
Diff
From a1126887f068def0bc11f5260e55e25b9c03e3ea Mon Sep 17 00:00:00 2001
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From: Marc Kleine-Budde <mkl@pengutronix.de>
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Date: Fri, 1 Mar 2019 09:18:54 +0100
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Subject: [PATCH] can: flexcan: rename struct
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flexcan_priv::reg_imask{1,2}_default to rx_mask{1,2}
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The flexcan IP core has up to 64 mailboxes, each one has a corresponding
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interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
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imask1 or imask2 registers.
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In the timestamp (i.e. non FIFO) mode the driver needs to mask out all
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non RX interrupt sources and uses the precomputed values
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reg_imask1_default and reg_imask2_default of struct flexcan_priv for
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this.
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However in the current driver the reg_imask{1,2}_default cannot be used
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directly to get the pending RX interrupts. The TX interrupt is part of
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these variables, so it needs to be masked out, too.
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This is a preparation patch to clean up calculation of the pending RX
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interrupts, it only renames the variables from
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reg_imask{1,2}_default
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to
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rx_mask{1,2}
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To better reflect their meaning after the complete conversion. This
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change is done with the following sed command:
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sed -i -e "s/reg_imask\(1\|2\)_default/rx_mask\1/" drivers/net/can/flexcan.c
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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---
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drivers/net/can/flexcan.c | 22 +++++++++++-----------
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1 file changed, 11 insertions(+), 11 deletions(-)
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--- a/drivers/net/can/flexcan.c
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+++ b/drivers/net/can/flexcan.c
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@@ -278,8 +278,8 @@ struct flexcan_priv {
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u8 clk_src; /* clock source of CAN Protocol Engine */
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u32 reg_ctrl_default;
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- u32 reg_imask1_default;
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- u32 reg_imask2_default;
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+ u32 rx_mask1;
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+ u32 rx_mask2;
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struct clk *clk_ipg;
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struct clk *clk_per;
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@@ -879,9 +879,9 @@ static inline u64 flexcan_read_reg_iflag
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struct flexcan_regs __iomem *regs = priv->regs;
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u32 iflag1, iflag2;
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- iflag2 = priv->read(®s->iflag2) & priv->reg_imask2_default &
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+ iflag2 = priv->read(®s->iflag2) & priv->rx_mask2 &
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~FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
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- iflag1 = priv->read(®s->iflag1) & priv->reg_imask1_default;
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+ iflag1 = priv->read(®s->iflag1) & priv->rx_mask1;
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return (u64)iflag2 << 32 | iflag1;
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}
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@@ -1228,8 +1228,8 @@ static int flexcan_chip_start(struct net
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/* enable interrupts atomically */
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disable_irq(dev->irq);
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priv->write(priv->reg_ctrl_default, ®s->ctrl);
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- priv->write(priv->reg_imask1_default, ®s->imask1);
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- priv->write(priv->reg_imask2_default, ®s->imask2);
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+ priv->write(priv->rx_mask1, ®s->imask1);
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+ priv->write(priv->rx_mask2, ®s->imask2);
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enable_irq(dev->irq);
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/* print chip status */
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@@ -1320,8 +1320,8 @@ static int flexcan_open(struct net_devic
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priv->tx_mb_idx = priv->mb_count - 1;
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priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
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- priv->reg_imask1_default = 0;
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- priv->reg_imask2_default = FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
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+ priv->rx_mask1 = 0;
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+ priv->rx_mask2 = FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
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priv->offload.mailbox_read = flexcan_mailbox_read;
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@@ -1333,12 +1333,12 @@ static int flexcan_open(struct net_devic
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imask = GENMASK_ULL(priv->offload.mb_last,
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priv->offload.mb_first);
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- priv->reg_imask1_default |= imask;
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- priv->reg_imask2_default |= imask >> 32;
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+ priv->rx_mask1 |= imask;
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+ priv->rx_mask2 |= imask >> 32;
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err = can_rx_offload_add_timestamp(dev, &priv->offload);
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} else {
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- priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
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+ priv->rx_mask1 |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
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FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
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err = can_rx_offload_add_fifo(dev, &priv->offload,
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FLEXCAN_NAPI_WEIGHT);
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