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451b51f0dc
Manual adapted the following patches:
generic/hack-5.15/221-module_exports.patch
bcm27xx/patches-5.15/950-0008-drm-vc4-hdmi-Use-a-mutex-to-prevent-concurrent-frame.patch
octeontx/patches-5.15/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 9693ed6a9e)
153 lines
6.1 KiB
Diff
153 lines
6.1 KiB
Diff
From 78936d46470938caa9a7ea529deeb36777b4f98e Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Wed, 16 Nov 2022 22:46:55 +0100
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Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for all parents
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It appears that having only .name populated in parent_data for clocks
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which are only globally searchable currently will not work as the clk core
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won't copy that name if there is no .fw_name present as well.
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So, populate .fw_name for all parent clocks in parent_data.
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Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
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Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20221116214655.1116467-1-robimarko@gmail.com
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---
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drivers/clk/qcom/gcc-ipq8074.c | 52 +++++++++++++++++-----------------
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1 file changed, 26 insertions(+), 26 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -675,7 +675,7 @@ static struct clk_rcg2 pcie0_aux_clk_src
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};
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static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
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- { .name = "pcie20_phy0_pipe_clk" },
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+ { .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
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{ .fw_name = "xo", .name = "xo" },
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};
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@@ -728,7 +728,7 @@ static struct clk_rcg2 pcie1_aux_clk_src
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};
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static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
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- { .name = "pcie20_phy1_pipe_clk" },
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+ { .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
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{ .fw_name = "xo", .name = "xo" },
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};
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@@ -1133,7 +1133,7 @@ static const struct freq_tbl ftbl_nss_no
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static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
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{ .fw_name = "xo", .name = "xo" },
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- { .name = "bias_pll_nss_noc_clk" },
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+ { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
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{ .hw = &gpll0.clkr.hw },
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{ .hw = &gpll2.clkr.hw },
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};
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@@ -1358,7 +1358,7 @@ static const struct freq_tbl ftbl_nss_pp
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static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
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{ .fw_name = "xo", .name = "xo" },
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- { .name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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{ .hw = &gpll0.clkr.hw },
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{ .hw = &gpll4.clkr.hw },
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{ .hw = &nss_crypto_pll.clkr.hw },
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@@ -1409,10 +1409,10 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
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{ .fw_name = "xo", .name = "xo" },
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- { .name = "uniphy0_gcc_rx_clk" },
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- { .name = "uniphy0_gcc_tx_clk" },
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+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
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+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
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@@ -1461,10 +1461,10 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
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{ .fw_name = "xo", .name = "xo" },
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- { .name = "uniphy0_gcc_tx_clk" },
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- { .name = "uniphy0_gcc_rx_clk" },
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+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
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+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
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@@ -1692,12 +1692,12 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
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{ .fw_name = "xo", .name = "xo" },
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- { .name = "uniphy0_gcc_rx_clk" },
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- { .name = "uniphy0_gcc_tx_clk" },
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- { .name = "uniphy1_gcc_rx_clk" },
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- { .name = "uniphy1_gcc_tx_clk" },
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+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
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+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
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+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
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+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map
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@@ -1754,12 +1754,12 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
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{ .fw_name = "xo", .name = "xo" },
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- { .name = "uniphy0_gcc_tx_clk" },
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- { .name = "uniphy0_gcc_rx_clk" },
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- { .name = "uniphy1_gcc_tx_clk" },
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- { .name = "uniphy1_gcc_rx_clk" },
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+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
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+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
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+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
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+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map
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@@ -1816,10 +1816,10 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
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{ .fw_name = "xo", .name = "xo" },
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- { .name = "uniphy2_gcc_rx_clk" },
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- { .name = "uniphy2_gcc_tx_clk" },
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+ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
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+ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
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@@ -1873,10 +1873,10 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
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{ .fw_name = "xo", .name = "xo" },
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- { .name = "uniphy2_gcc_tx_clk" },
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- { .name = "uniphy2_gcc_rx_clk" },
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+ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
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+ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
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