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openwrt/target/linux/ipq807x/patches-5.15/0047-v6.2-clk-qcom-ipq8074-convert-to-parent-data.patch
Hauke Mehrtens 451b51f0dc kernel: bump 5.15 to 5.15.155 
Manual adapted the following patches:
   generic/hack-5.15/221-module_exports.patch
   bcm27xx/patches-5.15/950-0008-drm-vc4-hdmi-Use-a-mutex-to-prevent-concurrent-frame.patch
   octeontx/patches-5.15/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 9693ed6a9e)
2024-04-30 23:38:26 +02:00

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From e6c5115d6845f25eda7e162dcd783a2044215867 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sun, 30 Oct 2022 18:57:01 +0100
Subject: [PATCH] clk: qcom: ipq8074: convert to parent data
Convert the IPQ8074 GCC driver to use parent data instead of global
name matching.
Utilize ARRAY_SIZE for num_parents instead of hardcoding the value.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221030175703.1103224-1-robimarko@gmail.com
---
drivers/clk/qcom/gcc-ipq8074.c | 1781 +++++++++++++++-----------------
1 file changed, 813 insertions(+), 968 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -49,349 +49,6 @@ enum {
P_UNIPHY2_TX,
};
-static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
- "xo",
- "gpll0",
- "gpll0_out_main_div2",
-};
-
-static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL0_DIV2, 4 },
-};
-
-static const struct parent_map gcc_xo_gpll0_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
-};
-
-static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
- "xo",
- "gpll0",
- "gpll2",
- "gpll0_out_main_div2",
-};
-
-static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL2, 2 },
- { P_GPLL0_DIV2, 4 },
-};
-
-static const char * const gcc_xo_gpll0_sleep_clk[] = {
- "xo",
- "gpll0",
- "sleep_clk",
-};
-
-static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 2 },
- { P_SLEEP_CLK, 6 },
-};
-
-static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
- "xo",
- "gpll6",
- "gpll0",
- "gpll0_out_main_div2",
-};
-
-static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
- { P_XO, 0 },
- { P_GPLL6, 1 },
- { P_GPLL0, 3 },
- { P_GPLL0_DIV2, 4 },
-};
-
-static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = {
- "xo",
- "gpll0_out_main_div2",
- "gpll0",
-};
-
-static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
- { P_XO, 0 },
- { P_GPLL0_DIV2, 2 },
- { P_GPLL0, 1 },
-};
-
-static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
- "usb3phy_0_cc_pipe_clk",
- "xo",
-};
-
-static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
- { P_USB3PHY_0_PIPE, 0 },
- { P_XO, 2 },
-};
-
-static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = {
- "usb3phy_1_cc_pipe_clk",
- "xo",
-};
-
-static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
- { P_USB3PHY_1_PIPE, 0 },
- { P_XO, 2 },
-};
-
-static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = {
- "pcie20_phy0_pipe_clk",
- "xo",
-};
-
-static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
- { P_PCIE20_PHY0_PIPE, 0 },
- { P_XO, 2 },
-};
-
-static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = {
- "pcie20_phy1_pipe_clk",
- "xo",
-};
-
-static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
- { P_PCIE20_PHY1_PIPE, 0 },
- { P_XO, 2 },
-};
-
-static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = {
- "xo",
- "gpll0",
- "gpll6",
- "gpll0_out_main_div2",
-};
-
-static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL6, 2 },
- { P_GPLL0_DIV2, 4 },
-};
-
-static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
- "xo",
- "gpll0",
- "gpll6",
- "gpll0_out_main_div2",
-};
-
-static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL6, 2 },
- { P_GPLL0_DIV2, 3 },
-};
-
-static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
- "xo",
- "bias_pll_nss_noc_clk",
- "gpll0",
- "gpll2",
-};
-
-static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
- { P_XO, 0 },
- { P_BIAS_PLL_NSS_NOC, 1 },
- { P_GPLL0, 2 },
- { P_GPLL2, 3 },
-};
-
-static const char * const gcc_xo_nss_crypto_pll_gpll0[] = {
- "xo",
- "nss_crypto_pll",
- "gpll0",
-};
-
-static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
- { P_XO, 0 },
- { P_NSS_CRYPTO_PLL, 1 },
- { P_GPLL0, 2 },
-};
-
-static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
- "xo",
- "ubi32_pll",
- "gpll0",
- "gpll2",
- "gpll4",
- "gpll6",
-};
-
-static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
- { P_XO, 0 },
- { P_UBI32_PLL, 1 },
- { P_GPLL0, 2 },
- { P_GPLL2, 3 },
- { P_GPLL4, 4 },
- { P_GPLL6, 5 },
-};
-
-static const char * const gcc_xo_gpll0_out_main_div2[] = {
- "xo",
- "gpll0_out_main_div2",
-};
-
-static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
- { P_XO, 0 },
- { P_GPLL0_DIV2, 1 },
-};
-
-static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
- "xo",
- "bias_pll_cc_clk",
- "gpll0",
- "gpll4",
- "nss_crypto_pll",
- "ubi32_pll",
-};
-
-static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
- { P_XO, 0 },
- { P_BIAS_PLL, 1 },
- { P_GPLL0, 2 },
- { P_GPLL4, 3 },
- { P_NSS_CRYPTO_PLL, 4 },
- { P_UBI32_PLL, 5 },
-};
-
-static const char * const gcc_xo_gpll0_gpll4[] = {
- "xo",
- "gpll0",
- "gpll4",
-};
-
-static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL4, 2 },
-};
-
-static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
- "xo",
- "uniphy0_gcc_rx_clk",
- "uniphy0_gcc_tx_clk",
- "ubi32_pll",
- "bias_pll_cc_clk",
-};
-
-static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
- { P_XO, 0 },
- { P_UNIPHY0_RX, 1 },
- { P_UNIPHY0_TX, 2 },
- { P_UBI32_PLL, 5 },
- { P_BIAS_PLL, 6 },
-};
-
-static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
- "xo",
- "uniphy0_gcc_tx_clk",
- "uniphy0_gcc_rx_clk",
- "ubi32_pll",
- "bias_pll_cc_clk",
-};
-
-static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
- { P_XO, 0 },
- { P_UNIPHY0_TX, 1 },
- { P_UNIPHY0_RX, 2 },
- { P_UBI32_PLL, 5 },
- { P_BIAS_PLL, 6 },
-};
-
-static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
- "xo",
- "uniphy0_gcc_rx_clk",
- "uniphy0_gcc_tx_clk",
- "uniphy1_gcc_rx_clk",
- "uniphy1_gcc_tx_clk",
- "ubi32_pll",
- "bias_pll_cc_clk",
-};
-
-static const struct parent_map
-gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
- { P_XO, 0 },
- { P_UNIPHY0_RX, 1 },
- { P_UNIPHY0_TX, 2 },
- { P_UNIPHY1_RX, 3 },
- { P_UNIPHY1_TX, 4 },
- { P_UBI32_PLL, 5 },
- { P_BIAS_PLL, 6 },
-};
-
-static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
- "xo",
- "uniphy0_gcc_tx_clk",
- "uniphy0_gcc_rx_clk",
- "uniphy1_gcc_tx_clk",
- "uniphy1_gcc_rx_clk",
- "ubi32_pll",
- "bias_pll_cc_clk",
-};
-
-static const struct parent_map
-gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
- { P_XO, 0 },
- { P_UNIPHY0_TX, 1 },
- { P_UNIPHY0_RX, 2 },
- { P_UNIPHY1_TX, 3 },
- { P_UNIPHY1_RX, 4 },
- { P_UBI32_PLL, 5 },
- { P_BIAS_PLL, 6 },
-};
-
-static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
- "xo",
- "uniphy2_gcc_rx_clk",
- "uniphy2_gcc_tx_clk",
- "ubi32_pll",
- "bias_pll_cc_clk",
-};
-
-static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
- { P_XO, 0 },
- { P_UNIPHY2_RX, 1 },
- { P_UNIPHY2_TX, 2 },
- { P_UBI32_PLL, 5 },
- { P_BIAS_PLL, 6 },
-};
-
-static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
- "xo",
- "uniphy2_gcc_tx_clk",
- "uniphy2_gcc_rx_clk",
- "ubi32_pll",
- "bias_pll_cc_clk",
-};
-
-static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
- { P_XO, 0 },
- { P_UNIPHY2_TX, 1 },
- { P_UNIPHY2_RX, 2 },
- { P_UBI32_PLL, 5 },
- { P_BIAS_PLL, 6 },
-};
-
-static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
- "xo",
- "gpll0",
- "gpll6",
- "gpll0_out_main_div2",
- "sleep_clk",
-};
-
-static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
- { P_XO, 0 },
- { P_GPLL0, 1 },
- { P_GPLL6, 2 },
- { P_GPLL0_DIV2, 4 },
- { P_SLEEP_CLK, 6 },
-};
-
static struct clk_alpha_pll gpll0_main = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
@@ -400,8 +57,9 @@ static struct clk_alpha_pll gpll0_main =
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_main",
- .parent_names = (const char *[]){
- "xo"
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ .name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
@@ -414,9 +72,8 @@ static struct clk_fixed_factor gpll0_out
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll0_out_main_div2",
- .parent_names = (const char *[]){
- "gpll0_main"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gpll0_main.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
@@ -428,9 +85,8 @@ static struct clk_alpha_pll_postdiv gpll
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
- .parent_names = (const char *[]){
- "gpll0_main"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gpll0_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
@@ -444,8 +100,9 @@ static struct clk_alpha_pll gpll2_main =
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gpll2_main",
- .parent_names = (const char *[]){
- "xo"
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ .name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
@@ -460,9 +117,8 @@ static struct clk_alpha_pll_postdiv gpll
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2",
- .parent_names = (const char *[]){
- "gpll2_main"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gpll2_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
@@ -476,8 +132,9 @@ static struct clk_alpha_pll gpll4_main =
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gpll4_main",
- .parent_names = (const char *[]){
- "xo"
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ .name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
@@ -492,9 +149,8 @@ static struct clk_alpha_pll_postdiv gpll
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
- .parent_names = (const char *[]){
- "gpll4_main"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gpll4_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
@@ -509,8 +165,9 @@ static struct clk_alpha_pll gpll6_main =
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll6_main",
- .parent_names = (const char *[]){
- "xo"
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ .name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
@@ -525,9 +182,8 @@ static struct clk_alpha_pll_postdiv gpll
.width = 2,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6",
- .parent_names = (const char *[]){
- "gpll6_main"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gpll6_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
@@ -538,9 +194,8 @@ static struct clk_fixed_factor gpll6_out
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll6_out_main_div2",
- .parent_names = (const char *[]){
- "gpll6_main"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gpll6_main.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
@@ -555,8 +210,9 @@ static struct clk_alpha_pll ubi32_pll_ma
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "ubi32_pll_main",
- .parent_names = (const char *[]){
- "xo"
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ .name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_huayra_ops,
@@ -570,9 +226,8 @@ static struct clk_alpha_pll_postdiv ubi3
.width = 2,
.clkr.hw.init = &(struct clk_init_data){
.name = "ubi32_pll",
- .parent_names = (const char *[]){
- "ubi32_pll_main"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &ubi32_pll_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -587,8 +242,9 @@ static struct clk_alpha_pll nss_crypto_p
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "nss_crypto_pll_main",
- .parent_names = (const char *[]){
- "xo"
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ .name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
@@ -602,9 +258,8 @@ static struct clk_alpha_pll_postdiv nss_
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_crypto_pll",
- .parent_names = (const char *[]){
- "nss_crypto_pll_main"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_crypto_pll_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
@@ -617,6 +272,18 @@ static const struct freq_tbl ftbl_pcnoc_
{ }
};
+static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .hw = &gpll0.clkr.hw},
+ { .hw = &gpll0_out_main_div2.hw},
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_DIV2, 4 },
+};
+
static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
.cmd_rcgr = 0x27000,
.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
@@ -624,8 +291,8 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcnoc_bfdcd_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
.flags = CLK_IS_CRITICAL,
},
@@ -636,9 +303,8 @@ static struct clk_fixed_factor pcnoc_clk
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "pcnoc_clk_src",
- .parent_names = (const char *[]){
- "pcnoc_bfdcd_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -652,8 +318,9 @@ static struct clk_branch gcc_sleep_clk_s
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_sleep_clk_src",
- .parent_names = (const char *[]){
- "sleep_clk"
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "sleep_clk",
+ .name = "sleep_clk",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -676,8 +343,8 @@ static struct clk_rcg2 blsp1_qup1_i2c_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -702,8 +369,8 @@ static struct clk_rcg2 blsp1_qup1_spi_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -715,8 +382,8 @@ static struct clk_rcg2 blsp1_qup2_i2c_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -729,8 +396,8 @@ static struct clk_rcg2 blsp1_qup2_spi_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -742,8 +409,8 @@ static struct clk_rcg2 blsp1_qup3_i2c_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -756,8 +423,8 @@ static struct clk_rcg2 blsp1_qup3_spi_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -769,8 +436,8 @@ static struct clk_rcg2 blsp1_qup4_i2c_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -783,8 +450,8 @@ static struct clk_rcg2 blsp1_qup4_spi_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -796,8 +463,8 @@ static struct clk_rcg2 blsp1_qup5_i2c_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -810,8 +477,8 @@ static struct clk_rcg2 blsp1_qup5_spi_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -823,8 +490,8 @@ static struct clk_rcg2 blsp1_qup6_i2c_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -837,8 +504,8 @@ static struct clk_rcg2 blsp1_qup6_spi_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -871,8 +538,8 @@ static struct clk_rcg2 blsp1_uart1_apps_
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -885,8 +552,8 @@ static struct clk_rcg2 blsp1_uart2_apps_
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -899,8 +566,8 @@ static struct clk_rcg2 blsp1_uart3_apps_
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -913,8 +580,8 @@ static struct clk_rcg2 blsp1_uart4_apps_
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart4_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -927,8 +594,8 @@ static struct clk_rcg2 blsp1_uart5_apps_
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart5_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -941,8 +608,8 @@ static struct clk_rcg2 blsp1_uart6_apps_
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart6_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -952,6 +619,11 @@ static const struct clk_parent_data gcc_
{ .hw = &gpll0.clkr.hw },
};
+static const struct parent_map gcc_xo_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+};
+
static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
@@ -966,7 +638,7 @@ static struct clk_rcg2 pcie0_axi_clk_src
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie0_axi_clk_src",
.parent_data = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -976,6 +648,18 @@ static const struct freq_tbl ftbl_pcie_a
{ }
};
+static const struct clk_parent_data gcc_xo_gpll0_sleep_clk[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .hw = &gpll0.clkr.hw },
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
+};
+
+static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 2 },
+ { P_SLEEP_CLK, 6 },
+};
+
static struct clk_rcg2 pcie0_aux_clk_src = {
.cmd_rcgr = 0x75024,
.freq_tbl = ftbl_pcie_aux_clk_src,
@@ -984,12 +668,22 @@ static struct clk_rcg2 pcie0_aux_clk_src
.parent_map = gcc_xo_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie0_aux_clk_src",
- .parent_names = gcc_xo_gpll0_sleep_clk,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
+static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
+ { .name = "pcie20_phy0_pipe_clk" },
+ { .fw_name = "xo", .name = "xo" },
+};
+
+static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
+ { P_PCIE20_PHY0_PIPE, 0 },
+ { P_XO, 2 },
+};
+
static struct clk_regmap_mux pcie0_pipe_clk_src = {
.reg = 0x7501c,
.shift = 8,
@@ -998,8 +692,8 @@ static struct clk_regmap_mux pcie0_pipe_
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "pcie0_pipe_clk_src",
- .parent_names = gcc_pcie20_phy0_pipe_clk_xo,
- .num_parents = 2,
+ .parent_data = gcc_pcie20_phy0_pipe_clk_xo,
+ .num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -1014,7 +708,7 @@ static struct clk_rcg2 pcie1_axi_clk_src
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie1_axi_clk_src",
.parent_data = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1027,12 +721,22 @@ static struct clk_rcg2 pcie1_aux_clk_src
.parent_map = gcc_xo_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie1_aux_clk_src",
- .parent_names = gcc_xo_gpll0_sleep_clk,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
+static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
+ { .name = "pcie20_phy1_pipe_clk" },
+ { .fw_name = "xo", .name = "xo" },
+};
+
+static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
+ { P_PCIE20_PHY1_PIPE, 0 },
+ { P_XO, 2 },
+};
+
static struct clk_regmap_mux pcie1_pipe_clk_src = {
.reg = 0x7601c,
.shift = 8,
@@ -1041,8 +745,8 @@ static struct clk_regmap_mux pcie1_pipe_
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "pcie1_pipe_clk_src",
- .parent_names = gcc_pcie20_phy1_pipe_clk_xo,
- .num_parents = 2,
+ .parent_data = gcc_pcie20_phy1_pipe_clk_xo,
+ .num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -1061,6 +765,20 @@ static const struct freq_tbl ftbl_sdcc_a
{ }
};
+static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2.clkr.hw },
+ { .hw = &gpll0_out_main_div2.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL2, 2 },
+ { P_GPLL0_DIV2, 4 },
+};
+
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x42004,
.freq_tbl = ftbl_sdcc_apps_clk_src,
@@ -1069,8 +787,8 @@ static struct clk_rcg2 sdcc1_apps_clk_sr
.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
- .num_parents = 4,
+ .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
.ops = &clk_rcg2_floor_ops,
},
};
@@ -1082,6 +800,20 @@ static const struct freq_tbl ftbl_sdcc_i
{ }
};
+static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll6.clkr.hw },
+ { .hw = &gpll0_out_main_div2.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL6, 2 },
+ { P_GPLL0_DIV2, 4 },
+};
+
static struct clk_rcg2 sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x5d000,
.freq_tbl = ftbl_sdcc_ice_core_clk_src,
@@ -1090,8 +822,8 @@ static struct clk_rcg2 sdcc1_ice_core_cl
.parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_ice_core_clk_src",
- .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2,
- .num_parents = 4,
+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -1104,8 +836,8 @@ static struct clk_rcg2 sdcc2_apps_clk_sr
.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
- .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
- .num_parents = 4,
+ .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
.ops = &clk_rcg2_floor_ops,
},
};
@@ -1117,6 +849,18 @@ static const struct freq_tbl ftbl_usb_ma
{ }
};
+static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .hw = &gpll0_out_main_div2.hw },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0_DIV2, 2 },
+ { P_GPLL0, 1 },
+};
+
static struct clk_rcg2 usb0_master_clk_src = {
.cmd_rcgr = 0x3e00c,
.freq_tbl = ftbl_usb_master_clk_src,
@@ -1125,8 +869,8 @@ static struct clk_rcg2 usb0_master_clk_s
.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb0_master_clk_src",
- .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1144,8 +888,8 @@ static struct clk_rcg2 usb0_aux_clk_src
.parent_map = gcc_xo_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb0_aux_clk_src",
- .parent_names = gcc_xo_gpll0_sleep_clk,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
@@ -1157,6 +901,20 @@ static const struct freq_tbl ftbl_usb_mo
{ }
};
+static const struct clk_parent_data gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .hw = &gpll6.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_out_main_div2.hw },
+};
+
+static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL6, 1 },
+ { P_GPLL0, 3 },
+ { P_GPLL0_DIV2, 4 },
+};
+
static struct clk_rcg2 usb0_mock_utmi_clk_src = {
.cmd_rcgr = 0x3e020,
.freq_tbl = ftbl_usb_mock_utmi_clk_src,
@@ -1165,12 +923,22 @@ static struct clk_rcg2 usb0_mock_utmi_cl
.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb0_mock_utmi_clk_src",
- .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
- .num_parents = 4,
+ .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
+static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
+ { .name = "usb3phy_0_cc_pipe_clk" },
+ { .fw_name = "xo", .name = "xo" },
+};
+
+static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
+ { P_USB3PHY_0_PIPE, 0 },
+ { P_XO, 2 },
+};
+
static struct clk_regmap_mux usb0_pipe_clk_src = {
.reg = 0x3e048,
.shift = 8,
@@ -1179,8 +947,8 @@ static struct clk_regmap_mux usb0_pipe_c
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "usb0_pipe_clk_src",
- .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo,
- .num_parents = 2,
+ .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
+ .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -1195,8 +963,8 @@ static struct clk_rcg2 usb1_master_clk_s
.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb1_master_clk_src",
- .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1209,8 +977,8 @@ static struct clk_rcg2 usb1_aux_clk_src
.parent_map = gcc_xo_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb1_aux_clk_src",
- .parent_names = gcc_xo_gpll0_sleep_clk,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
@@ -1223,12 +991,22 @@ static struct clk_rcg2 usb1_mock_utmi_cl
.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb1_mock_utmi_clk_src",
- .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
- .num_parents = 4,
+ .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
+static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
+ { .name = "usb3phy_1_cc_pipe_clk" },
+ { .fw_name = "xo", .name = "xo" },
+};
+
+static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
+ { P_USB3PHY_1_PIPE, 0 },
+ { P_XO, 2 },
+};
+
static struct clk_regmap_mux usb1_pipe_clk_src = {
.reg = 0x3f048,
.shift = 8,
@@ -1237,8 +1015,8 @@ static struct clk_regmap_mux usb1_pipe_c
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "usb1_pipe_clk_src",
- .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo,
- .num_parents = 2,
+ .parent_data = gcc_usb3phy_1_cc_pipe_clk_xo,
+ .num_parents = ARRAY_SIZE(gcc_usb3phy_1_cc_pipe_clk_xo),
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -1252,8 +1030,9 @@ static struct clk_branch gcc_xo_clk_src
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_xo_clk_src",
- .parent_names = (const char *[]){
- "xo"
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ .name = "xo",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
@@ -1267,9 +1046,8 @@ static struct clk_fixed_factor gcc_xo_di
.div = 4,
.hw.init = &(struct clk_init_data){
.name = "gcc_xo_div4_clk_src",
- .parent_names = (const char *[]){
- "gcc_xo_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1287,6 +1065,20 @@ static const struct freq_tbl ftbl_system
{ }
};
+static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll6.clkr.hw },
+ { .hw = &gpll0_out_main_div2.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL6, 2 },
+ { P_GPLL0_DIV2, 3 },
+};
+
static struct clk_rcg2 system_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x26004,
.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
@@ -1294,8 +1086,8 @@ static struct clk_rcg2 system_noc_bfdcd_
.parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_bfdcd_clk_src",
- .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
- .num_parents = 4,
+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
.flags = CLK_IS_CRITICAL,
},
@@ -1306,9 +1098,8 @@ static struct clk_fixed_factor system_no
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "system_noc_clk_src",
- .parent_names = (const char *[]){
- "system_noc_bfdcd_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &system_noc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1329,7 +1120,7 @@ static struct clk_rcg2 nss_ce_clk_src =
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ce_clk_src",
.parent_data = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1340,6 +1131,20 @@ static const struct freq_tbl ftbl_nss_no
{ }
};
+static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .name = "bias_pll_nss_noc_clk" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL_NSS_NOC, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL2, 3 },
+};
+
static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x68088,
.freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
@@ -1347,8 +1152,8 @@ static struct clk_rcg2 nss_noc_bfdcd_clk
.parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_noc_bfdcd_clk_src",
- .parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
- .num_parents = 4,
+ .parent_data = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
+ .num_parents = ARRAY_SIZE(gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2),
.ops = &clk_rcg2_ops,
},
};
@@ -1358,9 +1163,8 @@ static struct clk_fixed_factor nss_noc_c
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "nss_noc_clk_src",
- .parent_names = (const char *[]){
- "nss_noc_bfdcd_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_noc_bfdcd_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1373,6 +1177,18 @@ static const struct freq_tbl ftbl_nss_cr
{ }
};
+static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .hw = &nss_crypto_pll.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_NSS_CRYPTO_PLL, 1 },
+ { P_GPLL0, 2 },
+};
+
static struct clk_rcg2 nss_crypto_clk_src = {
.cmd_rcgr = 0x68144,
.freq_tbl = ftbl_nss_crypto_clk_src,
@@ -1381,8 +1197,8 @@ static struct clk_rcg2 nss_crypto_clk_sr
.parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_crypto_clk_src",
- .parent_names = gcc_xo_nss_crypto_pll_gpll0,
- .num_parents = 3,
+ .parent_data = gcc_xo_nss_crypto_pll_gpll0,
+ .num_parents = ARRAY_SIZE(gcc_xo_nss_crypto_pll_gpll0),
.ops = &clk_rcg2_ops,
},
};
@@ -1396,6 +1212,24 @@ static const struct freq_tbl ftbl_nss_ub
{ }
};
+static const struct clk_parent_data gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+ { .hw = &gpll6.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
+ { P_XO, 0 },
+ { P_UBI32_PLL, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL2, 3 },
+ { P_GPLL4, 4 },
+ { P_GPLL6, 5 },
+};
+
static struct clk_rcg2 nss_ubi0_clk_src = {
.cmd_rcgr = 0x68104,
.freq_tbl = ftbl_nss_ubi_clk_src,
@@ -1403,8 +1237,8 @@ static struct clk_rcg2 nss_ubi0_clk_src
.parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ubi0_clk_src",
- .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
- .num_parents = 6,
+ .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
+ .num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -1417,9 +1251,8 @@ static struct clk_regmap_div nss_ubi0_di
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_ubi0_div_clk_src",
- .parent_names = (const char *[]){
- "nss_ubi0_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ubi0_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1434,8 +1267,8 @@ static struct clk_rcg2 nss_ubi1_clk_src
.parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ubi1_clk_src",
- .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
- .num_parents = 6,
+ .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
+ .num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
@@ -1448,9 +1281,8 @@ static struct clk_regmap_div nss_ubi1_di
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_ubi1_div_clk_src",
- .parent_names = (const char *[]){
- "nss_ubi1_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ubi1_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1464,6 +1296,16 @@ static const struct freq_tbl ftbl_ubi_mp
{ }
};
+static const struct clk_parent_data gcc_xo_gpll0_out_main_div2[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .hw = &gpll0_out_main_div2.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0_DIV2, 1 },
+};
+
static struct clk_rcg2 ubi_mpt_clk_src = {
.cmd_rcgr = 0x68090,
.freq_tbl = ftbl_ubi_mpt_clk_src,
@@ -1471,8 +1313,8 @@ static struct clk_rcg2 ubi_mpt_clk_src =
.parent_map = gcc_xo_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "ubi_mpt_clk_src",
- .parent_names = gcc_xo_gpll0_out_main_div2,
- .num_parents = 2,
+ .parent_data = gcc_xo_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -1483,6 +1325,18 @@ static const struct freq_tbl ftbl_nss_im
{ }
};
+static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL4, 2 },
+};
+
static struct clk_rcg2 nss_imem_clk_src = {
.cmd_rcgr = 0x68158,
.freq_tbl = ftbl_nss_imem_clk_src,
@@ -1490,8 +1344,8 @@ static struct clk_rcg2 nss_imem_clk_src
.parent_map = gcc_xo_gpll0_gpll4_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_imem_clk_src",
- .parent_names = gcc_xo_gpll0_gpll4,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll4,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
.ops = &clk_rcg2_ops,
},
};
@@ -1502,6 +1356,24 @@ static const struct freq_tbl ftbl_nss_pp
{ }
};
+static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .name = "bias_pll_cc_clk" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+ { .hw = &nss_crypto_pll.clkr.hw },
+ { .hw = &ubi32_pll.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL4, 3 },
+ { P_NSS_CRYPTO_PLL, 4 },
+ { P_UBI32_PLL, 5 },
+};
+
static struct clk_rcg2 nss_ppe_clk_src = {
.cmd_rcgr = 0x68080,
.freq_tbl = ftbl_nss_ppe_clk_src,
@@ -1509,8 +1381,8 @@ static struct clk_rcg2 nss_ppe_clk_src =
.parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ppe_clk_src",
- .parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
- .num_parents = 6,
+ .parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
+ .num_parents = ARRAY_SIZE(gcc_xo_bias_gpll0_gpll4_nss_ubi32),
.ops = &clk_rcg2_ops,
},
};
@@ -1520,9 +1392,8 @@ static struct clk_fixed_factor nss_ppe_c
.div = 4,
.hw.init = &(struct clk_init_data){
.name = "nss_ppe_cdiv_clk_src",
- .parent_names = (const char *[]){
- "nss_ppe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1536,6 +1407,22 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
+static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .name = "uniphy0_gcc_rx_clk" },
+ { .name = "uniphy0_gcc_tx_clk" },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .name = "bias_pll_cc_clk" },
+};
+
+static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_RX, 1 },
+ { P_UNIPHY0_TX, 2 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
static struct clk_rcg2 nss_port1_rx_clk_src = {
.cmd_rcgr = 0x68020,
.freq_tbl = ftbl_nss_port1_rx_clk_src,
@@ -1543,8 +1430,8 @@ static struct clk_rcg2 nss_port1_rx_clk_
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port1_rx_clk_src",
- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
- .num_parents = 5,
+ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
@@ -1556,9 +1443,8 @@ static struct clk_regmap_div nss_port1_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port1_rx_div_clk_src",
- .parent_names = (const char *[]){
- "nss_port1_rx_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port1_rx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1573,6 +1459,22 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
+static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .name = "uniphy0_gcc_tx_clk" },
+ { .name = "uniphy0_gcc_rx_clk" },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .name = "bias_pll_cc_clk" },
+};
+
+static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_TX, 1 },
+ { P_UNIPHY0_RX, 2 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
static struct clk_rcg2 nss_port1_tx_clk_src = {
.cmd_rcgr = 0x68028,
.freq_tbl = ftbl_nss_port1_tx_clk_src,
@@ -1580,8 +1482,8 @@ static struct clk_rcg2 nss_port1_tx_clk_
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port1_tx_clk_src",
- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
- .num_parents = 5,
+ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
@@ -1593,9 +1495,8 @@ static struct clk_regmap_div nss_port1_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port1_tx_div_clk_src",
- .parent_names = (const char *[]){
- "nss_port1_tx_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port1_tx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1610,8 +1511,8 @@ static struct clk_rcg2 nss_port2_rx_clk_
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port2_rx_clk_src",
- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
- .num_parents = 5,
+ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
@@ -1623,9 +1524,8 @@ static struct clk_regmap_div nss_port2_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port2_rx_div_clk_src",
- .parent_names = (const char *[]){
- "nss_port2_rx_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port2_rx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1640,8 +1540,8 @@ static struct clk_rcg2 nss_port2_tx_clk_
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port2_tx_clk_src",
- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
- .num_parents = 5,
+ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
@@ -1653,9 +1553,8 @@ static struct clk_regmap_div nss_port2_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port2_tx_div_clk_src",
- .parent_names = (const char *[]){
- "nss_port2_tx_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port2_tx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1670,8 +1569,8 @@ static struct clk_rcg2 nss_port3_rx_clk_
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port3_rx_clk_src",
- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
- .num_parents = 5,
+ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
@@ -1683,9 +1582,8 @@ static struct clk_regmap_div nss_port3_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port3_rx_div_clk_src",
- .parent_names = (const char *[]){
- "nss_port3_rx_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port3_rx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1700,8 +1598,8 @@ static struct clk_rcg2 nss_port3_tx_clk_
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port3_tx_clk_src",
- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
- .num_parents = 5,
+ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
@@ -1713,9 +1611,8 @@ static struct clk_regmap_div nss_port3_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port3_tx_div_clk_src",
- .parent_names = (const char *[]){
- "nss_port3_tx_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port3_tx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1730,8 +1627,8 @@ static struct clk_rcg2 nss_port4_rx_clk_
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port4_rx_clk_src",
- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
- .num_parents = 5,
+ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
@@ -1743,9 +1640,8 @@ static struct clk_regmap_div nss_port4_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port4_rx_div_clk_src",
- .parent_names = (const char *[]){
- "nss_port4_rx_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port4_rx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1760,8 +1656,8 @@ static struct clk_rcg2 nss_port4_tx_clk_
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port4_tx_clk_src",
- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
- .num_parents = 5,
+ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
@@ -1773,9 +1669,8 @@ static struct clk_regmap_div nss_port4_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port4_tx_div_clk_src",
- .parent_names = (const char *[]){
- "nss_port4_tx_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port4_tx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1795,6 +1690,27 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
+static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .name = "uniphy0_gcc_rx_clk" },
+ { .name = "uniphy0_gcc_tx_clk" },
+ { .name = "uniphy1_gcc_rx_clk" },
+ { .name = "uniphy1_gcc_tx_clk" },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .name = "bias_pll_cc_clk" },
+};
+
+static const struct parent_map
+gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_RX, 1 },
+ { P_UNIPHY0_TX, 2 },
+ { P_UNIPHY1_RX, 3 },
+ { P_UNIPHY1_TX, 4 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
static struct clk_rcg2 nss_port5_rx_clk_src = {
.cmd_rcgr = 0x68060,
.freq_tbl = ftbl_nss_port5_rx_clk_src,
@@ -1802,8 +1718,8 @@ static struct clk_rcg2 nss_port5_rx_clk_
.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port5_rx_clk_src",
- .parent_names = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
- .num_parents = 7,
+ .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
@@ -1815,9 +1731,8 @@ static struct clk_regmap_div nss_port5_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port5_rx_div_clk_src",
- .parent_names = (const char *[]){
- "nss_port5_rx_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port5_rx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1837,6 +1752,27 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
+static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .name = "uniphy0_gcc_tx_clk" },
+ { .name = "uniphy0_gcc_rx_clk" },
+ { .name = "uniphy1_gcc_tx_clk" },
+ { .name = "uniphy1_gcc_rx_clk" },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .name = "bias_pll_cc_clk" },
+};
+
+static const struct parent_map
+gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_TX, 1 },
+ { P_UNIPHY0_RX, 2 },
+ { P_UNIPHY1_TX, 3 },
+ { P_UNIPHY1_RX, 4 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
static struct clk_rcg2 nss_port5_tx_clk_src = {
.cmd_rcgr = 0x68068,
.freq_tbl = ftbl_nss_port5_tx_clk_src,
@@ -1844,8 +1780,8 @@ static struct clk_rcg2 nss_port5_tx_clk_
.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port5_tx_clk_src",
- .parent_names = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
- .num_parents = 7,
+ .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
@@ -1857,9 +1793,8 @@ static struct clk_regmap_div nss_port5_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port5_tx_div_clk_src",
- .parent_names = (const char *[]){
- "nss_port5_tx_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port5_tx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1879,6 +1814,22 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
+static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .name = "uniphy2_gcc_rx_clk" },
+ { .name = "uniphy2_gcc_tx_clk" },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .name = "bias_pll_cc_clk" },
+};
+
+static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY2_RX, 1 },
+ { P_UNIPHY2_TX, 2 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
static struct clk_rcg2 nss_port6_rx_clk_src = {
.cmd_rcgr = 0x68070,
.freq_tbl = ftbl_nss_port6_rx_clk_src,
@@ -1886,8 +1837,8 @@ static struct clk_rcg2 nss_port6_rx_clk_
.parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port6_rx_clk_src",
- .parent_names = gcc_xo_uniphy2_rx_tx_ubi32_bias,
- .num_parents = 5,
+ .parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias,
+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
@@ -1899,9 +1850,8 @@ static struct clk_regmap_div nss_port6_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port6_rx_div_clk_src",
- .parent_names = (const char *[]){
- "nss_port6_rx_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port6_rx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1921,6 +1871,22 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
+static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .name = "uniphy2_gcc_tx_clk" },
+ { .name = "uniphy2_gcc_rx_clk" },
+ { .hw = &ubi32_pll.clkr.hw },
+ { .name = "bias_pll_cc_clk" },
+};
+
+static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY2_TX, 1 },
+ { P_UNIPHY2_RX, 2 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
static struct clk_rcg2 nss_port6_tx_clk_src = {
.cmd_rcgr = 0x68078,
.freq_tbl = ftbl_nss_port6_tx_clk_src,
@@ -1928,8 +1894,8 @@ static struct clk_rcg2 nss_port6_tx_clk_
.parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port6_tx_clk_src",
- .parent_names = gcc_xo_uniphy2_tx_rx_ubi32_bias,
- .num_parents = 5,
+ .parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias,
+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias),
.ops = &clk_rcg2_ops,
},
};
@@ -1941,9 +1907,8 @@ static struct clk_regmap_div nss_port6_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port6_tx_div_clk_src",
- .parent_names = (const char *[]){
- "nss_port6_tx_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port6_tx_clk_src.clkr.hw },
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1966,8 +1931,8 @@ static struct clk_rcg2 crypto_clk_src =
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "crypto_clk_src",
- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
- .num_parents = 3,
+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
.ops = &clk_rcg2_ops,
},
};
@@ -1977,6 +1942,22 @@ static struct freq_tbl ftbl_gp_clk_src[]
{ }
};
+static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
+ { .fw_name = "xo", .name = "xo" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll6.clkr.hw },
+ { .hw = &gpll0_out_main_div2.hw },
+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL6, 2 },
+ { P_GPLL0_DIV2, 4 },
+ { P_SLEEP_CLK, 6 },
+};
+
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x08004,
.freq_tbl = ftbl_gp_clk_src,
@@ -1985,8 +1966,8 @@ static struct clk_rcg2 gp1_clk_src = {
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
- .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
- .num_parents = 5,
+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
@@ -1999,8 +1980,8 @@ static struct clk_rcg2 gp2_clk_src = {
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
- .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
- .num_parents = 5,
+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
@@ -2013,8 +1994,8 @@ static struct clk_rcg2 gp3_clk_src = {
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
- .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
- .num_parents = 5,
+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
.ops = &clk_rcg2_ops,
},
};
@@ -2026,9 +2007,8 @@ static struct clk_branch gcc_blsp1_ahb_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2043,9 +2023,8 @@ static struct clk_branch gcc_blsp1_qup1_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup1_i2c_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2060,9 +2039,8 @@ static struct clk_branch gcc_blsp1_qup1_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup1_spi_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2077,9 +2055,8 @@ static struct clk_branch gcc_blsp1_qup2_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup2_i2c_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2094,9 +2071,8 @@ static struct clk_branch gcc_blsp1_qup2_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup2_spi_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2111,9 +2087,8 @@ static struct clk_branch gcc_blsp1_qup3_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup3_i2c_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2128,9 +2103,8 @@ static struct clk_branch gcc_blsp1_qup3_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup3_spi_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2145,9 +2119,8 @@ static struct clk_branch gcc_blsp1_qup4_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup4_i2c_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2162,9 +2135,8 @@ static struct clk_branch gcc_blsp1_qup4_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup4_spi_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2179,9 +2151,8 @@ static struct clk_branch gcc_blsp1_qup5_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup5_i2c_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2196,9 +2167,8 @@ static struct clk_branch gcc_blsp1_qup5_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup5_spi_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2213,9 +2183,8 @@ static struct clk_branch gcc_blsp1_qup6_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup6_i2c_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2230,9 +2199,8 @@ static struct clk_branch gcc_blsp1_qup6_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup6_spi_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2247,9 +2215,8 @@ static struct clk_branch gcc_blsp1_uart1
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart1_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_uart1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2264,9 +2231,8 @@ static struct clk_branch gcc_blsp1_uart2
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart2_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_uart2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2281,9 +2247,8 @@ static struct clk_branch gcc_blsp1_uart3
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart3_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_uart3_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2298,9 +2263,8 @@ static struct clk_branch gcc_blsp1_uart4
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart4_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_uart4_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2315,9 +2279,8 @@ static struct clk_branch gcc_blsp1_uart5
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart5_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart5_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_uart5_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2332,9 +2295,8 @@ static struct clk_branch gcc_blsp1_uart6
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart6_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart6_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_uart6_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2350,9 +2312,8 @@ static struct clk_branch gcc_prng_ahb_cl
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2367,9 +2328,8 @@ static struct clk_branch gcc_qpic_ahb_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qpic_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2384,9 +2344,8 @@ static struct clk_branch gcc_qpic_clk =
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qpic_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2401,9 +2360,8 @@ static struct clk_branch gcc_pcie0_ahb_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2418,9 +2376,8 @@ static struct clk_branch gcc_pcie0_aux_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_aux_clk",
- .parent_names = (const char *[]){
- "pcie0_aux_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcie0_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2435,9 +2392,8 @@ static struct clk_branch gcc_pcie0_axi_m
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_axi_m_clk",
- .parent_names = (const char *[]){
- "pcie0_axi_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcie0_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2452,9 +2408,8 @@ static struct clk_branch gcc_pcie0_axi_s
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_axi_s_clk",
- .parent_names = (const char *[]){
- "pcie0_axi_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcie0_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2470,9 +2425,8 @@ static struct clk_branch gcc_pcie0_pipe_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_pipe_clk",
- .parent_names = (const char *[]){
- "pcie0_pipe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcie0_pipe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2487,9 +2441,8 @@ static struct clk_branch gcc_sys_noc_pci
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_pcie0_axi_clk",
- .parent_names = (const char *[]){
- "pcie0_axi_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcie0_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2504,9 +2457,8 @@ static struct clk_branch gcc_pcie1_ahb_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2521,9 +2473,8 @@ static struct clk_branch gcc_pcie1_aux_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_aux_clk",
- .parent_names = (const char *[]){
- "pcie1_aux_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcie1_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2538,9 +2489,8 @@ static struct clk_branch gcc_pcie1_axi_m
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_axi_m_clk",
- .parent_names = (const char *[]){
- "pcie1_axi_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcie1_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2555,9 +2505,8 @@ static struct clk_branch gcc_pcie1_axi_s
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_axi_s_clk",
- .parent_names = (const char *[]){
- "pcie1_axi_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcie1_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2573,9 +2522,8 @@ static struct clk_branch gcc_pcie1_pipe_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_pipe_clk",
- .parent_names = (const char *[]){
- "pcie1_pipe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcie1_pipe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2590,9 +2538,8 @@ static struct clk_branch gcc_sys_noc_pci
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_pcie1_axi_clk",
- .parent_names = (const char *[]){
- "pcie1_axi_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcie1_axi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2607,9 +2554,8 @@ static struct clk_branch gcc_usb0_aux_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_aux_clk",
- .parent_names = (const char *[]){
- "usb0_aux_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &usb0_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2624,9 +2570,8 @@ static struct clk_branch gcc_sys_noc_usb
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb0_axi_clk",
- .parent_names = (const char *[]){
- "usb0_master_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &usb0_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2641,9 +2586,8 @@ static struct clk_branch gcc_usb0_master
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_master_clk",
- .parent_names = (const char *[]){
- "usb0_master_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &usb0_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2658,9 +2602,8 @@ static struct clk_branch gcc_usb0_mock_u
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_mock_utmi_clk",
- .parent_names = (const char *[]){
- "usb0_mock_utmi_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &usb0_mock_utmi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2675,9 +2618,8 @@ static struct clk_branch gcc_usb0_phy_cf
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_phy_cfg_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2693,9 +2635,8 @@ static struct clk_branch gcc_usb0_pipe_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_pipe_clk",
- .parent_names = (const char *[]){
- "usb0_pipe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &usb0_pipe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2710,9 +2651,8 @@ static struct clk_branch gcc_usb0_sleep_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_sleep_clk",
- .parent_names = (const char *[]){
- "gcc_sleep_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_sleep_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2727,9 +2667,8 @@ static struct clk_branch gcc_usb1_aux_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_aux_clk",
- .parent_names = (const char *[]){
- "usb1_aux_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &usb1_aux_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2744,9 +2683,8 @@ static struct clk_branch gcc_sys_noc_usb
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb1_axi_clk",
- .parent_names = (const char *[]){
- "usb1_master_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &usb1_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2761,9 +2699,8 @@ static struct clk_branch gcc_usb1_master
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_master_clk",
- .parent_names = (const char *[]){
- "usb1_master_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &usb1_master_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2778,9 +2715,8 @@ static struct clk_branch gcc_usb1_mock_u
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_mock_utmi_clk",
- .parent_names = (const char *[]){
- "usb1_mock_utmi_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &usb1_mock_utmi_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2795,9 +2731,8 @@ static struct clk_branch gcc_usb1_phy_cf
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_phy_cfg_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2813,9 +2748,8 @@ static struct clk_branch gcc_usb1_pipe_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_pipe_clk",
- .parent_names = (const char *[]){
- "usb1_pipe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &usb1_pipe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2830,9 +2764,8 @@ static struct clk_branch gcc_usb1_sleep_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_sleep_clk",
- .parent_names = (const char *[]){
- "gcc_sleep_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_sleep_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2847,9 +2780,8 @@ static struct clk_branch gcc_sdcc1_ahb_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2864,9 +2796,8 @@ static struct clk_branch gcc_sdcc1_apps_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
- .parent_names = (const char *[]){
- "sdcc1_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &sdcc1_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2881,9 +2812,8 @@ static struct clk_branch gcc_sdcc1_ice_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
- .parent_names = (const char *[]){
- "sdcc1_ice_core_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &sdcc1_ice_core_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2898,9 +2828,8 @@ static struct clk_branch gcc_sdcc2_ahb_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2915,9 +2844,8 @@ static struct clk_branch gcc_sdcc2_apps_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
- .parent_names = (const char *[]){
- "sdcc2_apps_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &sdcc2_apps_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2932,9 +2860,8 @@ static struct clk_branch gcc_mem_noc_nss
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mem_noc_nss_axi_clk",
- .parent_names = (const char *[]){
- "nss_noc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_noc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2949,9 +2876,8 @@ static struct clk_branch gcc_nss_ce_apb_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ce_apb_clk",
- .parent_names = (const char *[]){
- "nss_ce_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2966,9 +2892,8 @@ static struct clk_branch gcc_nss_ce_axi_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ce_axi_clk",
- .parent_names = (const char *[]){
- "nss_ce_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -2983,9 +2908,8 @@ static struct clk_branch gcc_nss_cfg_clk
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_cfg_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3000,9 +2924,8 @@ static struct clk_branch gcc_nss_crypto_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_crypto_clk",
- .parent_names = (const char *[]){
- "nss_crypto_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_crypto_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3017,9 +2940,8 @@ static struct clk_branch gcc_nss_csr_clk
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_csr_clk",
- .parent_names = (const char *[]){
- "nss_ce_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3034,9 +2956,8 @@ static struct clk_branch gcc_nss_edma_cf
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_edma_cfg_clk",
- .parent_names = (const char *[]){
- "nss_ppe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3051,9 +2972,8 @@ static struct clk_branch gcc_nss_edma_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_edma_clk",
- .parent_names = (const char *[]){
- "nss_ppe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3068,9 +2988,8 @@ static struct clk_branch gcc_nss_imem_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_imem_clk",
- .parent_names = (const char *[]){
- "nss_imem_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_imem_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3085,9 +3004,8 @@ static struct clk_branch gcc_nss_noc_clk
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_noc_clk",
- .parent_names = (const char *[]){
- "nss_noc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_noc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3102,9 +3020,8 @@ static struct clk_branch gcc_nss_ppe_btq
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_btq_clk",
- .parent_names = (const char *[]){
- "nss_ppe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3119,9 +3036,8 @@ static struct clk_branch gcc_nss_ppe_cfg
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_cfg_clk",
- .parent_names = (const char *[]){
- "nss_ppe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3136,9 +3052,8 @@ static struct clk_branch gcc_nss_ppe_clk
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_clk",
- .parent_names = (const char *[]){
- "nss_ppe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3153,9 +3068,8 @@ static struct clk_branch gcc_nss_ppe_ipe
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_ipe_clk",
- .parent_names = (const char *[]){
- "nss_ppe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3170,9 +3084,8 @@ static struct clk_branch gcc_nss_ptp_ref
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ptp_ref_clk",
- .parent_names = (const char *[]){
- "nss_ppe_cdiv_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ppe_cdiv_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3188,9 +3101,8 @@ static struct clk_branch gcc_crypto_ppe_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ppe_clk",
- .parent_names = (const char *[]){
- "nss_ppe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3205,9 +3117,8 @@ static struct clk_branch gcc_nssnoc_ce_a
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ce_apb_clk",
- .parent_names = (const char *[]){
- "nss_ce_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3222,9 +3133,8 @@ static struct clk_branch gcc_nssnoc_ce_a
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ce_axi_clk",
- .parent_names = (const char *[]){
- "nss_ce_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3239,9 +3149,8 @@ static struct clk_branch gcc_nssnoc_cryp
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_crypto_clk",
- .parent_names = (const char *[]){
- "nss_crypto_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_crypto_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3256,9 +3165,8 @@ static struct clk_branch gcc_nssnoc_ppe_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ppe_cfg_clk",
- .parent_names = (const char *[]){
- "nss_ppe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3273,9 +3181,8 @@ static struct clk_branch gcc_nssnoc_ppe_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ppe_clk",
- .parent_names = (const char *[]){
- "nss_ppe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3290,9 +3197,8 @@ static struct clk_branch gcc_nssnoc_qosg
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_qosgen_ref_clk",
- .parent_names = (const char *[]){
- "gcc_xo_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3307,9 +3213,8 @@ static struct clk_branch gcc_nssnoc_snoc
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_snoc_clk",
- .parent_names = (const char *[]){
- "system_noc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &system_noc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3324,9 +3229,8 @@ static struct clk_branch gcc_nssnoc_time
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_timeout_ref_clk",
- .parent_names = (const char *[]){
- "gcc_xo_div4_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_xo_div4_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3341,9 +3245,8 @@ static struct clk_branch gcc_nssnoc_ubi0
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ubi0_ahb_clk",
- .parent_names = (const char *[]){
- "nss_ce_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3358,9 +3261,8 @@ static struct clk_branch gcc_nssnoc_ubi1
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ubi1_ahb_clk",
- .parent_names = (const char *[]){
- "nss_ce_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3376,9 +3278,8 @@ static struct clk_branch gcc_ubi0_ahb_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_ahb_clk",
- .parent_names = (const char *[]){
- "nss_ce_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3394,9 +3295,8 @@ static struct clk_branch gcc_ubi0_axi_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_axi_clk",
- .parent_names = (const char *[]){
- "nss_noc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_noc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3412,9 +3312,8 @@ static struct clk_branch gcc_ubi0_nc_axi
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_nc_axi_clk",
- .parent_names = (const char *[]){
- "nss_noc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_noc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3430,9 +3329,8 @@ static struct clk_branch gcc_ubi0_core_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_core_clk",
- .parent_names = (const char *[]){
- "nss_ubi0_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ubi0_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3448,9 +3346,8 @@ static struct clk_branch gcc_ubi0_mpt_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_mpt_clk",
- .parent_names = (const char *[]){
- "ubi_mpt_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &ubi_mpt_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3466,9 +3363,8 @@ static struct clk_branch gcc_ubi1_ahb_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_ahb_clk",
- .parent_names = (const char *[]){
- "nss_ce_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ce_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3484,9 +3380,8 @@ static struct clk_branch gcc_ubi1_axi_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_axi_clk",
- .parent_names = (const char *[]){
- "nss_noc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_noc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3502,9 +3397,8 @@ static struct clk_branch gcc_ubi1_nc_axi
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_nc_axi_clk",
- .parent_names = (const char *[]){
- "nss_noc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_noc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3520,9 +3414,8 @@ static struct clk_branch gcc_ubi1_core_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_core_clk",
- .parent_names = (const char *[]){
- "nss_ubi1_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ubi1_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3538,9 +3431,8 @@ static struct clk_branch gcc_ubi1_mpt_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_mpt_clk",
- .parent_names = (const char *[]){
- "ubi_mpt_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &ubi_mpt_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3555,9 +3447,8 @@ static struct clk_branch gcc_cmn_12gpll_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cmn_12gpll_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3572,9 +3463,8 @@ static struct clk_branch gcc_cmn_12gpll_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cmn_12gpll_sys_clk",
- .parent_names = (const char *[]){
- "gcc_xo_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3589,9 +3479,8 @@ static struct clk_branch gcc_mdio_ahb_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdio_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3606,9 +3495,8 @@ static struct clk_branch gcc_uniphy0_ahb
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3623,9 +3511,8 @@ static struct clk_branch gcc_uniphy0_sys
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_sys_clk",
- .parent_names = (const char *[]){
- "gcc_xo_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3640,9 +3527,8 @@ static struct clk_branch gcc_uniphy1_ahb
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3657,9 +3543,8 @@ static struct clk_branch gcc_uniphy1_sys
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_sys_clk",
- .parent_names = (const char *[]){
- "gcc_xo_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3674,9 +3559,8 @@ static struct clk_branch gcc_uniphy2_ahb
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy2_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3691,9 +3575,8 @@ static struct clk_branch gcc_uniphy2_sys
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy2_sys_clk",
- .parent_names = (const char *[]){
- "gcc_xo_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_xo_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3708,9 +3591,8 @@ static struct clk_branch gcc_nss_port1_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port1_rx_clk",
- .parent_names = (const char *[]){
- "nss_port1_rx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port1_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3725,9 +3607,8 @@ static struct clk_branch gcc_nss_port1_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port1_tx_clk",
- .parent_names = (const char *[]){
- "nss_port1_tx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port1_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3742,9 +3623,8 @@ static struct clk_branch gcc_nss_port2_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port2_rx_clk",
- .parent_names = (const char *[]){
- "nss_port2_rx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port2_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3759,9 +3639,8 @@ static struct clk_branch gcc_nss_port2_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port2_tx_clk",
- .parent_names = (const char *[]){
- "nss_port2_tx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port2_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3776,9 +3655,8 @@ static struct clk_branch gcc_nss_port3_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port3_rx_clk",
- .parent_names = (const char *[]){
- "nss_port3_rx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port3_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3793,9 +3671,8 @@ static struct clk_branch gcc_nss_port3_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port3_tx_clk",
- .parent_names = (const char *[]){
- "nss_port3_tx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port3_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3810,9 +3687,8 @@ static struct clk_branch gcc_nss_port4_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port4_rx_clk",
- .parent_names = (const char *[]){
- "nss_port4_rx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port4_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3827,9 +3703,8 @@ static struct clk_branch gcc_nss_port4_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port4_tx_clk",
- .parent_names = (const char *[]){
- "nss_port4_tx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port4_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3844,9 +3719,8 @@ static struct clk_branch gcc_nss_port5_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port5_rx_clk",
- .parent_names = (const char *[]){
- "nss_port5_rx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port5_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3861,9 +3735,8 @@ static struct clk_branch gcc_nss_port5_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port5_tx_clk",
- .parent_names = (const char *[]){
- "nss_port5_tx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port5_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3878,9 +3751,8 @@ static struct clk_branch gcc_nss_port6_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port6_rx_clk",
- .parent_names = (const char *[]){
- "nss_port6_rx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port6_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3895,9 +3767,8 @@ static struct clk_branch gcc_nss_port6_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port6_tx_clk",
- .parent_names = (const char *[]){
- "nss_port6_tx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port6_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3912,9 +3783,8 @@ static struct clk_branch gcc_port1_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port1_mac_clk",
- .parent_names = (const char *[]){
- "nss_ppe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3929,9 +3799,8 @@ static struct clk_branch gcc_port2_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port2_mac_clk",
- .parent_names = (const char *[]){
- "nss_ppe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3946,9 +3815,8 @@ static struct clk_branch gcc_port3_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port3_mac_clk",
- .parent_names = (const char *[]){
- "nss_ppe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3963,9 +3831,8 @@ static struct clk_branch gcc_port4_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port4_mac_clk",
- .parent_names = (const char *[]){
- "nss_ppe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3980,9 +3847,8 @@ static struct clk_branch gcc_port5_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port5_mac_clk",
- .parent_names = (const char *[]){
- "nss_ppe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -3997,9 +3863,8 @@ static struct clk_branch gcc_port6_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port6_mac_clk",
- .parent_names = (const char *[]){
- "nss_ppe_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_ppe_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4014,9 +3879,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port1_rx_clk",
- .parent_names = (const char *[]){
- "nss_port1_rx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port1_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4031,9 +3895,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port1_tx_clk",
- .parent_names = (const char *[]){
- "nss_port1_tx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port1_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4048,9 +3911,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port2_rx_clk",
- .parent_names = (const char *[]){
- "nss_port2_rx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port2_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4065,9 +3927,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port2_tx_clk",
- .parent_names = (const char *[]){
- "nss_port2_tx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port2_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4082,9 +3943,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port3_rx_clk",
- .parent_names = (const char *[]){
- "nss_port3_rx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port3_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4099,9 +3959,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port3_tx_clk",
- .parent_names = (const char *[]){
- "nss_port3_tx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port3_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4116,9 +3975,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port4_rx_clk",
- .parent_names = (const char *[]){
- "nss_port4_rx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port4_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4133,9 +3991,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port4_tx_clk",
- .parent_names = (const char *[]){
- "nss_port4_tx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port4_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4150,9 +4007,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port5_rx_clk",
- .parent_names = (const char *[]){
- "nss_port5_rx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port5_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4167,9 +4023,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port5_tx_clk",
- .parent_names = (const char *[]){
- "nss_port5_tx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port5_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4184,9 +4039,8 @@ static struct clk_branch gcc_uniphy1_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_port5_rx_clk",
- .parent_names = (const char *[]){
- "nss_port5_rx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port5_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4201,9 +4055,8 @@ static struct clk_branch gcc_uniphy1_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_port5_tx_clk",
- .parent_names = (const char *[]){
- "nss_port5_tx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port5_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4218,9 +4071,8 @@ static struct clk_branch gcc_uniphy2_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy2_port6_rx_clk",
- .parent_names = (const char *[]){
- "nss_port6_rx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port6_rx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4235,9 +4087,8 @@ static struct clk_branch gcc_uniphy2_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy2_port6_tx_clk",
- .parent_names = (const char *[]){
- "nss_port6_tx_div_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &nss_port6_tx_div_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4253,9 +4104,8 @@ static struct clk_branch gcc_crypto_ahb_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ahb_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4271,9 +4121,8 @@ static struct clk_branch gcc_crypto_axi_
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_axi_clk",
- .parent_names = (const char *[]){
- "pcnoc_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &pcnoc_clk_src.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4289,9 +4138,8 @@ static struct clk_branch gcc_crypto_clk
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_clk",
- .parent_names = (const char *[]){
- "crypto_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &crypto_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4306,9 +4154,8 @@ static struct clk_branch gcc_gp1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
- .parent_names = (const char *[]){
- "gp1_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gp1_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4323,9 +4170,8 @@ static struct clk_branch gcc_gp2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
- .parent_names = (const char *[]){
- "gp2_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gp2_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4340,9 +4186,8 @@ static struct clk_branch gcc_gp3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
- .parent_names = (const char *[]){
- "gp3_clk_src"
- },
+ .parent_hws = (const struct clk_hw *[]){
+ &gp3_clk_src.clkr.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
@@ -4364,7 +4209,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie0_rchng_clk_src",
.parent_data = gcc_xo_gpll0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
.ops = &clk_rcg2_ops,
},
};
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