mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-28 01:28:59 +00:00
de7535a6ac
Deleted (upstreamed): generic/pending-5.15/850-0003-PCI-aardvark-Fix-support-for-MSI-interrupts.patch [1] [1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.34&id=60eabd66d17fa2cbc31f670b2f201f0bc54090a2 Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
60 lines
2.4 KiB
Diff
60 lines
2.4 KiB
Diff
From 7d8dc1f7cd007a7ce94c5b4c20d63a8b8d6d7751 Mon Sep 17 00:00:00 2001
|
|
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
|
|
Date: Tue, 30 Nov 2021 18:29:06 +0100
|
|
Subject: [PATCH] PCI: aardvark: Clear all MSIs at setup
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
We already clear all the other interrupts (ISR0, ISR1, HOST_CTRL_INT).
|
|
|
|
Define a new macro PCIE_MSI_ALL_MASK and do the same clearing for MSIs,
|
|
to ensure that we don't start receiving spurious interrupts.
|
|
|
|
Use this new mask in advk_pcie_handle_msi();
|
|
|
|
Link: https://lore.kernel.org/r/20211130172913.9727-5-kabel@kernel.org
|
|
Signed-off-by: Pali Rohár <pali@kernel.org>
|
|
Signed-off-by: Marek Behún <kabel@kernel.org>
|
|
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
|
---
|
|
drivers/pci/controller/pci-aardvark.c | 6 ++++--
|
|
1 file changed, 4 insertions(+), 2 deletions(-)
|
|
|
|
--- a/drivers/pci/controller/pci-aardvark.c
|
|
+++ b/drivers/pci/controller/pci-aardvark.c
|
|
@@ -115,6 +115,7 @@
|
|
#define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
|
|
#define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
|
|
#define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
|
|
+#define PCIE_MSI_ALL_MASK GENMASK(31, 0)
|
|
#define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
|
|
#define PCIE_MSI_DATA_MASK GENMASK(15, 0)
|
|
|
|
@@ -570,6 +571,7 @@ static void advk_pcie_setup_hw(struct ad
|
|
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
|
|
|
|
/* Clear all interrupts */
|
|
+ advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
|
|
advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
|
|
advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
|
|
advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
|
|
@@ -582,7 +584,7 @@ static void advk_pcie_setup_hw(struct ad
|
|
advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
|
|
|
|
/* Unmask all MSIs */
|
|
- advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
|
|
+ advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
|
|
|
|
/* Enable summary interrupt for GIC SPI source */
|
|
reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
|
|
@@ -1389,7 +1391,7 @@ static void advk_pcie_handle_msi(struct
|
|
|
|
msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
|
|
msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
|
|
- msi_status = msi_val & ~msi_mask;
|
|
+ msi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK);
|
|
|
|
for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
|
|
if (!(BIT(msi_idx) & msi_status))
|