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ab7cabd09d
Compile-tested on: ramips/mt7621, x86/64. Run-tested on: ramips/mt7621. Signed-off-by: Stijn Segers <foss@volatilesystems.org>
171 lines
6.1 KiB
Diff
171 lines
6.1 KiB
Diff
From 830574225e621809600902b69bbdd563e67ef4eb Mon Sep 17 00:00:00 2001
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From: Chaotian Jing <chaotian.jing@mediatek.com>
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Date: Mon, 16 Oct 2017 09:46:33 +0800
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Subject: [PATCH 154/224] mmc: mediatek: add async fifo and data tune support
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mt2701/mt2712 supports async fifo & data tune, which can improve
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host stability.
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Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
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Tested-by: Sean Wang <sean.wang@mediatek.com>
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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---
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drivers/mmc/host/mtk-sd.c | 52 +++++++++++++++++++++++++++++++++++++++++++++--
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1 file changed, 50 insertions(+), 2 deletions(-)
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--- a/drivers/mmc/host/mtk-sd.c
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+++ b/drivers/mmc/host/mtk-sd.c
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@@ -74,6 +74,7 @@
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#define MSDC_DMA_CFG 0x9c
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#define MSDC_PATCH_BIT 0xb0
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#define MSDC_PATCH_BIT1 0xb4
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+#define MSDC_PATCH_BIT2 0xb8
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#define MSDC_PAD_TUNE 0xec
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#define MSDC_PAD_TUNE0 0xf0
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#define PAD_DS_TUNE 0x188
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@@ -216,11 +217,20 @@
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#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
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#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
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+#define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
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+#define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */
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+#define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */
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+#define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */
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+#define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */
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+
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#define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */
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#define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
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#define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
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#define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */
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#define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */
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+#define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */
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+#define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */
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+#define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */
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#define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
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#define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
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@@ -294,6 +304,7 @@ struct msdc_save_para {
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u32 pad_tune;
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u32 patch_bit0;
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u32 patch_bit1;
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+ u32 patch_bit2;
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u32 pad_ds_tune;
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u32 pad_cmd_tune;
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u32 emmc50_cfg0;
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@@ -303,6 +314,8 @@ struct mtk_mmc_compatible {
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u8 clk_div_bits;
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bool hs400_tune; /* only used for MT8173 */
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u32 pad_tune_reg;
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+ bool async_fifo;
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+ bool data_tune;
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};
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struct msdc_tune_para {
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@@ -365,24 +378,32 @@ static const struct mtk_mmc_compatible m
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.clk_div_bits = 8,
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.hs400_tune = false,
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.pad_tune_reg = MSDC_PAD_TUNE,
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+ .async_fifo = false,
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+ .data_tune = false,
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};
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static const struct mtk_mmc_compatible mt8173_compat = {
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.clk_div_bits = 8,
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.hs400_tune = true,
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.pad_tune_reg = MSDC_PAD_TUNE,
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+ .async_fifo = false,
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+ .data_tune = false,
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};
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static const struct mtk_mmc_compatible mt2701_compat = {
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.clk_div_bits = 12,
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.hs400_tune = false,
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.pad_tune_reg = MSDC_PAD_TUNE0,
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+ .async_fifo = true,
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+ .data_tune = true,
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};
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static const struct mtk_mmc_compatible mt2712_compat = {
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.clk_div_bits = 12,
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.hs400_tune = false,
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.pad_tune_reg = MSDC_PAD_TUNE0,
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+ .async_fifo = true,
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+ .data_tune = true,
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};
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static const struct of_device_id msdc_of_ids[] = {
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@@ -1252,8 +1273,29 @@ static void msdc_init_hw(struct msdc_hos
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sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
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writel(0x403c0046, host->base + MSDC_PATCH_BIT);
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sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
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- writel(0xffff0089, host->base + MSDC_PATCH_BIT1);
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+ writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
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sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
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+ if (host->dev_comp->async_fifo) {
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+ sdr_set_field(host->base + MSDC_PATCH_BIT2,
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+ MSDC_PB2_RESPWAIT, 3);
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+ sdr_set_field(host->base + MSDC_PATCH_BIT2,
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+ MSDC_PB2_RESPSTSENSEL, 2);
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+ sdr_set_field(host->base + MSDC_PATCH_BIT2,
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+ MSDC_PB2_CRCSTSENSEL, 2);
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+ /* use async fifo, then no need tune internal delay */
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+ sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
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+ MSDC_PATCH_BIT2_CFGRESP);
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+ sdr_set_bits(host->base + MSDC_PATCH_BIT2,
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+ MSDC_PATCH_BIT2_CFGCRCSTS);
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+ }
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+
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+ if (host->dev_comp->data_tune) {
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+ sdr_set_bits(host->base + tune_reg,
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+ MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
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+ } else {
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+ /* choose clock tune */
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+ sdr_set_bits(host->base + tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
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+ }
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/* Configure to enable SDIO mode.
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* it's must otherwise sdio cmd5 failed
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@@ -1268,6 +1310,8 @@ static void msdc_init_hw(struct msdc_hos
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host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
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host->def_tune_para.pad_tune = readl(host->base + tune_reg);
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+ host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
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+ host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
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dev_dbg(host->dev, "init hardware done!");
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}
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@@ -1480,7 +1524,7 @@ skip_fall:
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final_fall_delay.final_phase);
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final_delay = final_fall_delay.final_phase;
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}
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- if (host->hs200_cmd_int_delay)
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+ if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
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goto skip_internal;
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for (i = 0; i < PAD_DELAY_MAX; i++) {
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@@ -1638,6 +1682,8 @@ static int msdc_prepare_hs400_tuning(str
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host->hs400_mode = true;
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writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
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+ /* hs400 mode must set it to 0 */
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+ sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
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return 0;
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}
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@@ -1876,6 +1922,7 @@ static void msdc_save_reg(struct msdc_ho
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host->save_para.pad_tune = readl(host->base + tune_reg);
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host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
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host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
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+ host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
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host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
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host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
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host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
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@@ -1891,6 +1938,7 @@ static void msdc_restore_reg(struct msdc
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writel(host->save_para.pad_tune, host->base + tune_reg);
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writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
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writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
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+ writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
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writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
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writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
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writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
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