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This series of upstream patches properly implement a clock and reset driver for old ralink SoCs[1]. And it includes some related fixes[2] and improvements[3][4]. All patches have been merged into linux-next. They will be part of upcoming Linux 6.5. In order to switch to the new system controller driver, all clocks and resets properties in SoC dtsi have been updated, and kernel symbol "CONFIG_CLK_MTMIPS" have been added to the kernel config files. [1] https://lore.kernel.org/all/20230619040941.1340372-1-sergio.paracuellos@gmail.com [2] https://lore.kernel.org/all/20230622-mips-ralink-clk-wuninitialized-v1-1-ea9041240d10@kernel.org [3] https://lore.kernel.org/all/OSYP286MB03120BABB25900E113ED42B7BC5CA@OSYP286MB0312.JPNP286.PROD.OUTLOOK.COM [4] https://lore.kernel.org/all/TYAP286MB03151148AF8C054621DD55C3BC23A@TYAP286MB0315.JPNP286.PROD.OUTLOOK.COM Tested on Motorola MWR03 (MT7628) Tested on Haier HW-L1W (MT7620) Signed-off-by: Shiji Yang <yangshiji66@qq.com>
86 lines
2.7 KiB
Diff
86 lines
2.7 KiB
Diff
From 7cd1bb48885449a9323c7ff0f10012925e93b4e1 Mon Sep 17 00:00:00 2001
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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Date: Mon, 19 Jun 2023 06:09:37 +0200
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Subject: [PATCH 5/9] mips: ralink: rt3883: remove clock related code
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A properly clock driver for ralink SoCs has been added. Hence there is no
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need to have clock related code in 'arch/mips/ralink' folder anymore.
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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---
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arch/mips/include/asm/mach-ralink/rt3883.h | 8 ------
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arch/mips/ralink/rt3883.c | 44 ------------------------------
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2 files changed, 52 deletions(-)
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--- a/arch/mips/include/asm/mach-ralink/rt3883.h
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+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
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@@ -90,14 +90,6 @@
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#define RT3883_REVID_VER_ID_SHIFT 8
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#define RT3883_REVID_ECO_ID_MASK 0x0f
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-#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
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-#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
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-#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
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-#define RT3883_SYSCFG0_CPUCLK_250 0x0
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-#define RT3883_SYSCFG0_CPUCLK_384 0x1
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-#define RT3883_SYSCFG0_CPUCLK_480 0x2
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-#define RT3883_SYSCFG0_CPUCLK_500 0x3
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-
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#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
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#define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
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#define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)
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--- a/arch/mips/ralink/rt3883.c
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+++ b/arch/mips/ralink/rt3883.c
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@@ -17,50 +17,6 @@
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#include "common.h"
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-void __init ralink_clk_init(void)
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-{
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- unsigned long cpu_rate, sys_rate;
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- u32 syscfg0;
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- u32 clksel;
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- u32 ddr2;
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-
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- syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
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- clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
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- RT3883_SYSCFG0_CPUCLK_MASK);
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- ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
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-
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- switch (clksel) {
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- case RT3883_SYSCFG0_CPUCLK_250:
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- cpu_rate = 250000000;
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- sys_rate = (ddr2) ? 125000000 : 83000000;
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- break;
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- case RT3883_SYSCFG0_CPUCLK_384:
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- cpu_rate = 384000000;
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- sys_rate = (ddr2) ? 128000000 : 96000000;
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- break;
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- case RT3883_SYSCFG0_CPUCLK_480:
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- cpu_rate = 480000000;
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- sys_rate = (ddr2) ? 160000000 : 120000000;
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- break;
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- case RT3883_SYSCFG0_CPUCLK_500:
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- cpu_rate = 500000000;
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- sys_rate = (ddr2) ? 166000000 : 125000000;
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- break;
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- }
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-
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- ralink_clk_add("cpu", cpu_rate);
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- ralink_clk_add("10000100.timer", sys_rate);
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- ralink_clk_add("10000120.watchdog", sys_rate);
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- ralink_clk_add("10000500.uart", 40000000);
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- ralink_clk_add("10000900.i2c", 40000000);
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- ralink_clk_add("10000a00.i2s", 40000000);
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- ralink_clk_add("10000b00.spi", sys_rate);
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- ralink_clk_add("10000b40.spi", sys_rate);
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- ralink_clk_add("10000c00.uartlite", 40000000);
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- ralink_clk_add("10100000.ethernet", sys_rate);
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- ralink_clk_add("10180000.wmac", 40000000);
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-}
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-
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void __init ralink_of_remap(void)
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{
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rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
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