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02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
180 lines
3.9 KiB
Diff
180 lines
3.9 KiB
Diff
From 63495b04141e60ceb40d4632a41b7cd4a3d23dd2 Mon Sep 17 00:00:00 2001
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From: Kumar Gala <galak@codeaurora.org>
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Date: Wed, 28 May 2014 12:01:29 -0500
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Subject: [PATCH 091/182] ARM: dts: qcom: Update msm8974/apq8074 device trees
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* Move SoC peripherals into an SoC container node
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* Move serial enabling into board file (qcom-apq8074-dragonboard.dts)
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* Move spi pinctrl into board file
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* Cleanup cpu node to match binding spec, enable-method and compatible
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should be per cpu, not part of the container
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* Drop interrupts property from l2-cache node as its not part of the
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binding spec
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* Move timer node out of SoC container
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 28 +++++++++++++-
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arch/arm/boot/dts/qcom-msm8974.dtsi | 49 +++++++++---------------
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2 files changed, 45 insertions(+), 32 deletions(-)
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--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
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+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
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@@ -4,7 +4,11 @@
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model = "Qualcomm APQ8074 Dragonboard";
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compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
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- soc: soc {
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+ soc {
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+ serial@f991e000 {
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+ status = "ok";
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+ };
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+
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sdhci@f9824900 {
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bus-width = <8>;
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non-removable;
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@@ -15,5 +19,27 @@
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cd-gpios = <&msmgpio 62 0x1>;
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bus-width = <4>;
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};
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+
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+
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+ pinctrl@fd510000 {
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+ spi8_default: spi8_default {
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+ mosi {
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+ pins = "gpio45";
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+ function = "blsp_spi8";
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+ };
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+ miso {
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+ pins = "gpio46";
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+ function = "blsp_spi8";
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+ };
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+ cs {
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+ pins = "gpio47";
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+ function = "blsp_spi8";
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+ };
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+ clk {
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+ pins = "gpio48";
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+ function = "blsp_spi8";
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+ };
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+ };
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
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+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
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@@ -13,10 +13,10 @@
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <1 9 0xf04>;
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- compatible = "qcom,krait";
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- enable-method = "qcom,kpss-acc-v2";
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cpu@0 {
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+ compatible = "qcom,krait";
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+ enable-method = "qcom,kpss-acc-v2";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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@@ -24,6 +24,8 @@
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};
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cpu@1 {
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+ compatible = "qcom,krait";
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+ enable-method = "qcom,kpss-acc-v2";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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@@ -31,6 +33,8 @@
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};
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cpu@2 {
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+ compatible = "qcom,krait";
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+ enable-method = "qcom,kpss-acc-v2";
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device_type = "cpu";
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reg = <2>;
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next-level-cache = <&L2>;
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@@ -38,6 +42,8 @@
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};
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cpu@3 {
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+ compatible = "qcom,krait";
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+ enable-method = "qcom,kpss-acc-v2";
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device_type = "cpu";
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reg = <3>;
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next-level-cache = <&L2>;
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@@ -47,7 +53,6 @@
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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- interrupts = <0 2 0x4>;
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qcom,saw = <&saw_l2>;
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};
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};
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@@ -57,6 +62,15 @@
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interrupts = <1 7 0xf04>;
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};
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+ timer {
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+ compatible = "arm,armv7-timer";
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+ interrupts = <1 2 0xf08>,
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+ <1 3 0xf08>,
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+ <1 4 0xf08>,
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+ <1 1 0xf08>;
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+ clock-frequency = <19200000>;
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+ };
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+
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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@@ -71,15 +85,6 @@
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<0xf9002000 0x1000>;
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};
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- timer {
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- compatible = "arm,armv7-timer";
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- interrupts = <1 2 0xf08>,
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- <1 3 0xf08>,
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- <1 4 0xf08>,
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- <1 1 0xf08>;
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- clock-frequency = <19200000>;
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- };
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-
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timer@f9020000 {
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#address-cells = <1>;
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#size-cells = <1>;
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@@ -190,6 +195,7 @@
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interrupts = <0 108 0x0>;
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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+ status = "disabled";
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};
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sdhci@f9824900 {
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@@ -229,25 +235,6 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 208 0>;
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-
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- spi8_default: spi8_default {
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- mosi {
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- pins = "gpio45";
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- function = "blsp_spi8";
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- };
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- miso {
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- pins = "gpio46";
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- function = "blsp_spi8";
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- };
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- cs {
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- pins = "gpio47";
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- function = "blsp_spi8";
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- };
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- clk {
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- pins = "gpio48";
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- function = "blsp_spi8";
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- };
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- };
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};
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};
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};
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