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758c88b969
Fix some ugly whitepsaces and codestyle issues around the realtek sources. While this is by no means perfect, it catches what it caught. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
142 lines
2.7 KiB
ArmAsm
142 lines
2.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Realtek RTL839X SRAM clock setters
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* Copyright (C) 2022 Markus Stockhausen <markus.stockhausen@gmx.de>
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*/
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#include <asm/mipsregs.h>
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#include <dt-bindings/clock/rtl83xx-clk.h>
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#include "clk-rtl83xx.h"
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#define rGLB $t0
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#define rCTR $t1
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#define rMSK $t2
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#define rSLP1 $t3
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#define rSLP2 $t4
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#define rSLP3 $t5
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#define rTMP $t6
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#define rCP0 $t7
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.set noreorder
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.globl rtcl_839x_dram_start
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rtcl_839x_dram_start:
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/*
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* Functions start here and should avoid access to normal memory. REMARK! Do not forget about
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* stack pointer and dirty caches that might interfere.
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*/
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.globl rtcl_839x_dram_set_rate
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.ent rtcl_839x_dram_set_rate
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rtcl_839x_dram_set_rate:
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#ifdef CONFIG_RTL839X
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/* disable MIPS 34K branch and return prediction */
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mfc0 rCP0, CP0_CONFIG, 7
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ori rTMP, rCP0, 0xc
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mtc0 rTMP, CP0_CONFIG, 7
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li rCTR, RTL_SW_CORE_BASE
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addiu rGLB, rCTR, RTL839X_PLL_GLB_CTRL
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ori rTMP, $0, CLK_CPU
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beq $a0, rTMP, pre_cpu
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ori rTMP, $0, CLK_MEM
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beq $a0, rTMP, pre_mem
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nop
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pre_lxb:
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li rSLP1, 0x400000
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li rSLP2, 0x400000
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li rSLP3, 0x400000
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addiu rCTR, rCTR, RTL839X_PLL_LXB_CTRL0
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b main_set
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ori rMSK, $0, RTL839X_GLB_CTRL_LXB_CLKSEL_MASK
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pre_mem:
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/* try to avoid memory access with simple 64K data cache flush */
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li rMSK, RTL_SRAM_BASE
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li rTMP, 2048
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pre_flush:
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lw $0, 0(rMSK)
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addiu rMSK, rMSK, 32
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addiu rTMP, rTMP, -1
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bne rTMP, $0, pre_flush
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lw $0, -4(rMSK)
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li rSLP1, 0x10000
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li rSLP2, 0x10000
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li rSLP3, 0x10000
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addiu rCTR, rCTR, RTL839X_PLL_MEM_CTRL0
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b main_set
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ori rMSK, $0, RTL839X_GLB_CTRL_MEM_CLKSEL_MASK
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pre_cpu:
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li rSLP1, 0x1000
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li rSLP2, 0x1000
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li rSLP3, 0x200
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addiu rCTR, rCTR, RTL839X_PLL_CPU_CTRL0
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ori rMSK, $0, RTL839X_GLB_CTRL_CPU_CLKSEL_MASK
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main_set:
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/* switch to fixed clock */
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sync
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lw rTMP, 0(rGLB)
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sync
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or rTMP, rTMP, rMSK
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sync
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sw rTMP, 0(rGLB)
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/* wait until fixed clock in use */
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or rTMP, rSLP1, $0
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wait_fixclock:
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bnez rTMP, wait_fixclock
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addiu rTMP, rTMP, -1
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/* set new PLL values */
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sync
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sw $a1, 0(rCTR)
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sw $a2, 4(rCTR)
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sync
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/* wait for value takeover */
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or rTMP, rSLP2, $0
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wait_pll:
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bnez rTMP, wait_pll
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addiu rTMP, rTMP, -1
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/* switch back to PLL clock*/
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nor rMSK, rMSK, $0
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sync
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lw rTMP, 0(rGLB)
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sync
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and rTMP, rTMP, rMSK
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sync
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sw rTMP, 0(rGLB)
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/* wait until PLL clock in use */
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or rTMP, rSLP3, $0
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wait_pllclock:
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bnez rTMP, wait_pllclock
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addiu rTMP, rTMP, -1
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/* restore branch prediction */
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mtc0 rCP0, CP0_CONFIG, 7
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jr $ra
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nop
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#else /* !CONFIG_RTL839X */
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jr $ra
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nop
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#endif
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.end rtcl_839x_dram_set_rate
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/*
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* End marker. Do not delete.
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*/
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.word RTL_SRAM_MARKER
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.globl rtcl_839x_dram_size
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rtcl_839x_dram_size:
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.word .-rtcl_839x_dram_start
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