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c948a4782b
The DWR-960 Wireless Router is based on the MT7620A SoC. Specification: - MediaTek MT7620A (580 Mhz) - 128 MB of RAM - 16 MB of FLASH - 1x 802.11bgn radio - 1x 802.11ac radio (MT7610 mpcie card) - 4x 10/100 Mbps Ethernet (1 WAN and 3 LAN) - 1x 10/100/1000 Mbps Ethernet (1 LAN) (AR8035) - 2x internal, non-detachable antennas (Wifi 2.4G) - 3x external, detachable antennas (2x LTE, 1x Wifi 5G) - 1x LTE modem - UART (J4) header on PCB (57600 8n1) - 9x LED, 2x button - JBOOT bootloader Known issues: - Flash is extremely slow. Installation: Apply factory image via http web-gui or JBOOT recovery page How to revert to OEM firmware: - push the reset button and turn on the power. Wait until LED start blinking (~10sec.) - upload original factory image via JBOOT http (IP: 192.168.123.254) Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
191 lines
3.0 KiB
Plaintext
191 lines
3.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#include "mt7620a.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "dlink,dwr-960", "ralink,mt7620a-soc";
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model = "D-Link DWR-960";
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aliases {
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led-boot = &led_status;
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led-failsafe = &led_status;
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led-running = &led_status;
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led-upgrade = &led_status;
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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wps {
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label = "wps";
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gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_status: status {
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label = "dwr-960:green:status";
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gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
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};
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wan {
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label = "dwr-960:green:wan";
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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};
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lan {
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label = "dwr-960:green:lan";
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gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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};
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sms {
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label = "dwr-960:green:sms";
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gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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};
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signal_green {
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label = "dwr-960:green:signal";
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gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
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};
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signal_red {
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label = "dwr-960:red:signal";
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gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
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};
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4g {
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label = "dwr-960:green:4g";
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gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
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};
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3g {
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label = "dwr-960:green:3g";
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gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
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};
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wlan5g {
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label = "dwr-960:green:wlan5g";
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gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy0tpt";
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};
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wlan2g {
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label = "dwr-960:green:wlan2g";
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gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy1tpt";
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};
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};
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};
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ðernet {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii2_pins &mdio_pins>;
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mediatek,portmap = "wllll";
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port@5 {
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status = "okay";
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phy-mode = "rgmii-txid";
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phy-handle = <&phy7>;
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};
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mdio-bus {
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status = "okay";
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phy7: ethernet-phy@7 {
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reg = <7>;
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phy-mode = "rgmii-id";
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};
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};
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&gpio3 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <50000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "jboot";
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reg = <0x0 0x10000>;
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read-only;
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};
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partition@10000 {
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compatible = "amit,jimage";
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label = "firmware";
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reg = <0x10000 0xfe0000>;
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};
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config: partition@ff0000 {
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label = "config";
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reg = <0xff0000 0x10000>;
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read-only;
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};
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};
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};
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};
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&ehci {
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status = "okay";
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};
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&ohci {
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status = "okay";
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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wifi@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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ieee80211-freq-limit = <5000000 6000000>;
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mediatek,mtd-eeprom = <&config 0xe08e>;
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mtd-mac-address = <&config 0xe50e>;
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mtd-mac-address-increment = <2>;
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};
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};
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&state_default {
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default {
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ralink,group = "i2c", "wled", "spi refclk", "uartf", "ephy";
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ralink,function = "gpio";
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};
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};
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