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In current state there's huge regression on ipq806x target that causes the device to transmit broken/malformed frames that are not corrected/detected by error control mechanisms and other less severe issues. https://bugs.lede-project.org/index.php?do=details&task_id=1197 This finally had been narrowed down to patch 0071-pcie-qcom-fixes.patch Meanwhile QSDK contains a handful of commits that add support for ipq806x to upstream qcom pcie driver https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/log/drivers/pci/host/pcie-qcom.c?h=eggplant Unfortunately qca developers do not bother to push it upstream. Using those commits instead of lede 0071 patch fixes mentioned issue and probably many others as it seems that corrupted data has been originating within pcie misconfiguration. Fixes: FS#1197 and probably others Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
70 lines
2.0 KiB
Diff
70 lines
2.0 KiB
Diff
From edff8f777c6321ca89bb950a382f409c4a126e28 Mon Sep 17 00:00:00 2001
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From: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
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Date: Thu, 15 Dec 2016 17:38:18 +0530
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Subject: pcie: Set PCIE MRRS and MPS to 256B
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Set Max Read Request Size and Max Payload Size to 256 bytes,
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per chip team recommendation.
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Change-Id: I097004be2ced1b3096ffc10c318aae0b2bb155e8
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Signed-off-by: Gokul Sriram Palanisamy <gpalan@codeaurora.org>
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---
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drivers/pci/host/pcie-qcom.c | 37 +++++++++++++++++++++++++++++++++++++
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1 file changed, 37 insertions(+)
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(limited to 'drivers/pci/host/pcie-qcom.c')
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--- a/drivers/pci/host/pcie-qcom.c
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+++ b/drivers/pci/host/pcie-qcom.c
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@@ -92,6 +92,14 @@
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#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0
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+#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
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+#define __mask(a, b) (((1 << ((a) + 1)) - 1) & ~((1 << (b)) - 1))
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+#define PCIE20_DEV_CAS 0x78
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+#define PCIE20_MRRS_MASK __mask(14, 12)
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+#define PCIE20_MRRS(x) __set(x, 14, 12)
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+#define PCIE20_MPS_MASK __mask(7, 5)
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+#define PCIE20_MPS(x) __set(x, 7, 5)
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+
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struct qcom_pcie_resources_v0 {
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struct clk *iface_clk;
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struct clk *core_clk;
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@@ -745,6 +753,35 @@ static int qcom_pcie_probe(struct platfo
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return 0;
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}
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+static void qcom_pcie_fixup_final(struct pci_dev *dev)
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+{
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+ int cap, err;
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+ u16 ctl, reg_val;
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+
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+ cap = pci_pcie_cap(dev);
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+ if (!cap)
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+ return;
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+
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+ err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
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+
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+ if (err)
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+ return;
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+
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+ reg_val = ctl;
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+
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+ if (((reg_val & PCIE20_MRRS_MASK) >> 12) > 1)
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+ reg_val = (reg_val & ~(PCIE20_MRRS_MASK)) | PCIE20_MRRS(0x1);
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+
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+ if (((ctl & PCIE20_MPS_MASK) >> 5) > 1)
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+ reg_val = (reg_val & ~(PCIE20_MPS_MASK)) | PCIE20_MPS(0x1);
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+
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+ err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, reg_val);
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+
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+ if (err)
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+ pr_err("pcie config write failed %d\n", err);
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+}
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+DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, qcom_pcie_fixup_final);
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+
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static const struct of_device_id qcom_pcie_match[] = {
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{ .compatible = "qcom,pcie-ipq8064", .data = &ops_v0 },
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{ .compatible = "qcom,pcie-apq8064", .data = &ops_v0 },
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