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https://github.com/openwrt/openwrt.git
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87 lines
2.6 KiB
Diff
87 lines
2.6 KiB
Diff
From 49293bbc50cb7d44223eb49e0f7cb38e7dac2361 Mon Sep 17 00:00:00 2001
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From: Aleksander Jan Bajkowski <olek2@wp.pl>
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Date: Tue, 14 Sep 2021 23:21:01 +0200
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Subject: [PATCH 4/5] MIPS: lantiq: dma: make the burst length configurable by
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the drivers
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Make the burst length configurable by the drivers.
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Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
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Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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.../include/asm/mach-lantiq/xway/xway_dma.h | 2 +-
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arch/mips/lantiq/xway/dma.c | 38 ++++++++++++++++---
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2 files changed, 34 insertions(+), 6 deletions(-)
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--- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
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+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
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@@ -45,6 +45,6 @@ extern void ltq_dma_close(struct ltq_dma
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extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch);
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extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch);
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extern void ltq_dma_free(struct ltq_dma_channel *ch);
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-extern void ltq_dma_init_port(int p);
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+extern void ltq_dma_init_port(int p, int tx_burst, int rx_burst);
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#endif
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--- a/arch/mips/lantiq/xway/dma.c
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+++ b/arch/mips/lantiq/xway/dma.c
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@@ -181,7 +181,7 @@ ltq_dma_free(struct ltq_dma_channel *ch)
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EXPORT_SYMBOL_GPL(ltq_dma_free);
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void
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-ltq_dma_init_port(int p)
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+ltq_dma_init_port(int p, int tx_burst, int rx_burst)
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{
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ltq_dma_w32(p, LTQ_DMA_PS);
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switch (p) {
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@@ -190,16 +190,44 @@ ltq_dma_init_port(int p)
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* Tell the DMA engine to swap the endianness of data frames and
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* drop packets if the channel arbitration fails.
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*/
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- ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,
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+ ltq_dma_w32_mask(0, (DMA_ETOP_ENDIANNESS | DMA_PDEN),
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LTQ_DMA_PCTRL);
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break;
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- case DMA_PORT_DEU:
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- ltq_dma_w32((DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT) |
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- (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),
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+ default:
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+ break;
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+ }
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+
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+ switch (rx_burst) {
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+ case 8:
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+ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_8W_BURST << DMA_RX_BURST_SHIFT),
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LTQ_DMA_PCTRL);
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break;
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+ case 4:
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+ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_4W_BURST << DMA_RX_BURST_SHIFT),
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+ LTQ_DMA_PCTRL);
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+ break;
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+ case 2:
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+ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),
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+ LTQ_DMA_PCTRL);
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+ break;
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+ default:
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+ break;
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+ }
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+ switch (tx_burst) {
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+ case 8:
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+ ltq_dma_w32_mask(0x30, (DMA_PCTRL_8W_BURST << DMA_TX_BURST_SHIFT),
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+ LTQ_DMA_PCTRL);
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+ break;
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+ case 4:
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+ ltq_dma_w32_mask(0x30, (DMA_PCTRL_4W_BURST << DMA_TX_BURST_SHIFT),
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+ LTQ_DMA_PCTRL);
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+ break;
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+ case 2:
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+ ltq_dma_w32_mask(0x30, (DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT),
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+ LTQ_DMA_PCTRL);
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+ break;
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default:
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break;
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}
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