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2d6cedab27
https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.1.92 Removed upstreamed: bcm27xx/patches-6.1/950-0270-net-bcmgenet-Reset-RBUF-on-first-open.patch generic/backport-6.1/600-v6.9-03-net-gro-add-flush-check-in-udp_gro_receive_segment.patch generic/pending-6.1/681-net-bridge-fix-multicast-to-unicast-with-fraglist-GS.patch generic/pending-6.1/682-net-core-reject-skb_copy-_expand-for-fraglist-GSO-sk.patch generic/pending-6.1/684-net-bridge-fix-corrupted-ethernet-header-on-multicas.patch generic/pending-6.1/778-net-l2tp-drop-flow-hash-on-forward.patch imx/patches-6.1/002-6.2-phy-freescale-imx8m-pcie-Refine-i.MX8MM-PCIe-PHY-dri.patch All other patches automatically rebased. Signed-off-by: Zxl hhyccc <zxlhhy@gmail.com>
100 lines
3.1 KiB
Diff
100 lines
3.1 KiB
Diff
From bf03b9281b119bcdc167b2dd6ac98294587eb5ff Mon Sep 17 00:00:00 2001
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From: Richard Zhu <hongxing.zhu@nxp.com>
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Date: Thu, 13 Oct 2022 09:47:02 +0800
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Subject: [PATCH 3/3] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support
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Add i.MX8MP PCIe PHY support.
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Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
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Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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Tested-by: Marek Vasut <marex@denx.de>
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Tested-by: Richard Leitner <richard.leitner@skidata.com>
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Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
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Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
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Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
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---
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drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 25 ++++++++++++++++++++--
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1 file changed, 23 insertions(+), 2 deletions(-)
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--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
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+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
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@@ -48,6 +48,7 @@
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enum imx8_pcie_phy_type {
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IMX8MM,
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+ IMX8MP,
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};
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struct imx8_pcie_phy_drvdata {
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@@ -60,6 +61,7 @@ struct imx8_pcie_phy {
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struct clk *clk;
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struct phy *phy;
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struct regmap *iomuxc_gpr;
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+ struct reset_control *perst;
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struct reset_control *reset;
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u32 refclk_pad_mode;
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u32 tx_deemph_gen1;
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@@ -74,11 +76,11 @@ static int imx8_pcie_phy_power_on(struct
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u32 val, pad_mode;
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struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy);
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- reset_control_assert(imx8_phy->reset);
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-
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pad_mode = imx8_phy->refclk_pad_mode;
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switch (imx8_phy->drvdata->variant) {
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case IMX8MM:
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+ reset_control_assert(imx8_phy->reset);
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+
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/* Tune PHY de-emphasis setting to pass PCIe compliance. */
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if (imx8_phy->tx_deemph_gen1)
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writel(imx8_phy->tx_deemph_gen1,
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@@ -87,6 +89,8 @@ static int imx8_pcie_phy_power_on(struct
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writel(imx8_phy->tx_deemph_gen2,
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imx8_phy->base + PCIE_PHY_TRSV_REG6);
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break;
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+ case IMX8MP: /* Do nothing. */
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+ break;
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}
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if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
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@@ -143,6 +147,9 @@ static int imx8_pcie_phy_power_on(struct
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IMX8MM_GPR_PCIE_CMN_RST);
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switch (imx8_phy->drvdata->variant) {
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+ case IMX8MP:
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+ reset_control_deassert(imx8_phy->perst);
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+ fallthrough;
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case IMX8MM:
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reset_control_deassert(imx8_phy->reset);
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usleep_range(200, 500);
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@@ -183,8 +190,14 @@ static const struct imx8_pcie_phy_drvdat
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.variant = IMX8MM,
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};
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+static const struct imx8_pcie_phy_drvdata imx8mp_drvdata = {
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+ .gpr = "fsl,imx8mp-iomuxc-gpr",
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+ .variant = IMX8MP,
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+};
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+
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static const struct of_device_id imx8_pcie_phy_of_match[] = {
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{.compatible = "fsl,imx8mm-pcie-phy", .data = &imx8mm_drvdata, },
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+ {.compatible = "fsl,imx8mp-pcie-phy", .data = &imx8mp_drvdata, },
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{ },
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};
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MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
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@@ -240,6 +253,14 @@ static int imx8_pcie_phy_probe(struct pl
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return PTR_ERR(imx8_phy->reset);
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}
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+ if (imx8_phy->drvdata->variant == IMX8MP) {
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+ imx8_phy->perst =
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+ devm_reset_control_get_exclusive(dev, "perst");
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+ if (IS_ERR(imx8_phy->perst))
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+ dev_err_probe(dev, PTR_ERR(imx8_phy->perst),
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+ "Failed to get PCIE PHY PERST control\n");
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+ }
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+
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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imx8_phy->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(imx8_phy->base))
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