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c5a399f372
Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.
This is behaviour of downstream driver as well, however I
haven't observed bug reports about this SoC in the wild, so this
commit's purpose is to align this chip with all other SoC's - MT7620
were already using this arrangement.
Fixes: 60fadae62b ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
356 lines
5.9 KiB
Plaintext
356 lines
5.9 KiB
Plaintext
/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
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aliases {
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spi0 = &spi0;
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serial0 = &uartlite;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mips,mips24KEc";
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reg = <0>;
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};
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};
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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cpuintc: cpuintc {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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palmbus: palmbus@10000000 {
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compatible = "palmbus";
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reg = <0x10000000 0x200000>;
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ranges = <0x0 0x10000000 0x1FFFFF>;
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#address-cells = <1>;
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#size-cells = <1>;
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sysc: syscon@0 {
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compatible = "ralink,rt3050-sysc", "syscon";
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reg = <0x0 0x100>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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timer: timer@100 {
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compatible = "ralink,rt3050-timer", "ralink,rt2880-timer";
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reg = <0x100 0x20>;
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clocks = <&sysc 3>;
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interrupt-parent = <&intc>;
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interrupts = <1>;
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};
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watchdog: watchdog@120 {
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compatible = "ralink,rt3050-wdt", "ralink,rt2880-wdt";
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reg = <0x120 0x10>;
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clocks = <&sysc 4>;
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resets = <&sysc 8>;
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reset-names = "wdt";
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interrupt-parent = <&intc>;
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interrupts = <1>;
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};
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intc: intc@200 {
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compatible = "ralink,rt3050-intc", "ralink,rt2880-intc";
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reg = <0x200 0x100>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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memc: memc@300 {
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compatible = "ralink,rt3050-memc";
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reg = <0x300 0x100>;
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interrupt-parent = <&intc>;
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interrupts = <3>;
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};
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uart: uart@500 {
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compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a";
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reg = <0x500 0x100>;
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clocks = <&sysc 5>;
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resets = <&sysc 12>;
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interrupt-parent = <&intc>;
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interrupts = <5>;
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reg-shift = <2>;
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status = "disabled";
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};
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gpio0: gpio@600 {
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compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
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reg = <0x600 0x34>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <24>;
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ralink,gpio-base = <0>;
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ralink,register-map = [ 00 04 08 0c
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20 24 28 2c
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30 34 ];
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interrupt-parent = <&intc>;
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interrupts = <6>;
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};
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gpio1: gpio@638 {
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compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
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reg = <0x638 0x24>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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ralink,gpio-base = <24>;
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ralink,register-map = [ 00 04 08 0c
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10 14 18 1c
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20 24 ];
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status = "disabled";
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};
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gpio2: gpio@660 {
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compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
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reg = <0x660 0x24>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <12>;
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ralink,gpio-base = <40>;
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ralink,register-map = [ 00 04 08 0c
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10 14 18 1c
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20 24 ];
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status = "disabled";
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};
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gdma: gdma@700 {
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compatible = "ralink,rt305x-gdma";
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reg = <0x700 0x100>;
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resets = <&sysc 14>;
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reset-names = "dma";
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interrupt-parent = <&intc>;
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interrupts = <7>;
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <8>;
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status = "disabled";
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};
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i2c@900 {
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compatible = "ralink,rt2880-i2c";
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reg = <0x900 0x100>;
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clocks = <&sysc 6>;
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resets = <&sysc 16>;
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reset-names = "i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c_pins>;
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};
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i2s@a00 {
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compatible = "ralink,rt3050-i2s";
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reg = <0xa00 0x100>;
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clocks = <&sysc 7>;
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resets = <&sysc 17>;
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reset-names = "i2s";
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interrupt-parent = <&intc>;
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interrupts = <10>;
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txdma-req = <2>;
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dmas = <&gdma 4>;
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dma-names = "tx";
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status = "disabled";
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};
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spi0: spi@b00 {
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compatible = "ralink,rt3050-spi", "ralink,rt2880-spi";
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reg = <0xb00 0x100>;
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resets = <&sysc 18>;
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reset-names = "spi";
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clocks = <&sysc 8>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins>;
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status = "disabled";
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};
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uartlite: uartlite@c00 {
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compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a";
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reg = <0xc00 0x100>;
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clocks = <&sysc 10>;
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resets = <&sysc 19>;
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interrupt-parent = <&intc>;
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interrupts = <12>;
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reg-shift = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&uartlite_pins>;
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};
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};
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pinctrl: pinctrl {
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compatible = "ralink,rt2880-pinmux";
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinctrl0 {
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sdram {
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groups = "sdram";
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function = "sdram";
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};
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};
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i2c_pins: i2c_pins {
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i2c_pins {
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groups = "i2c";
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function = "i2c";
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};
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};
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spi_pins: spi_pins {
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spi_pins {
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groups = "spi";
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function = "spi";
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};
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};
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rgmii_pins: rgmii {
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rgmii {
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groups = "rgmii";
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function = "rgmii";
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};
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};
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uartlite_pins: uartlite {
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uart {
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groups = "uartlite";
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function = "uartlite";
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};
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};
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};
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usbphy: usbphy {
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compatible = "ralink,rt3050-usbphy";
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#phy-cells = <0>;
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ralink,sysctl = <&sysc>;
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resets = <&sysc 22>;
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reset-names = "host";
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};
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ethernet: ethernet@10100000 {
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compatible = "ralink,rt3050-eth";
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reg = <0x10100000 0x10000>;
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clocks = <&sysc 11>;
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resets = <&sysc 21>, <&sysc 23>;
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reset-names = "fe", "esw";
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interrupt-parent = <&cpuintc>;
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interrupts = <5>;
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mediatek,switch = <&esw>;
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};
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esw: esw@10110000 {
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compatible = "ralink,rt3050-esw";
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reg = <0x10110000 0x8000>;
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resets = <&sysc 24>;
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reset-names = "ephy";
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interrupt-parent = <&intc>;
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interrupts = <17>;
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};
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wmac: wmac@10180000 {
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compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac";
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reg = <0x10180000 0x40000>;
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clocks = <&sysc 12>;
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interrupt-parent = <&cpuintc>;
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interrupts = <6>;
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ralink,eeprom = "soc_wmac.eeprom";
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};
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otg: otg@101c0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "ralink,rt3050-otg", "snps,dwc2";
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reg = <0x101c0000 0x40000>;
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interrupt-parent = <&intc>;
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interrupts = <18>;
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resets = <&sysc 22>;
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reset-names = "otg";
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status = "disabled";
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otg_port1: port@1 {
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reg = <1>;
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#trigger-source-cells = <0>;
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};
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};
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};
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