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25afe99b31
the support is still WIP. next steps are to make the pmic and ethernet work. this is the first commit to make sure nothing gets lost. Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 47354
54 lines
1.5 KiB
Diff
54 lines
1.5 KiB
Diff
From e75f8b666c976aff2aa30b967f74df021d800993 Mon Sep 17 00:00:00 2001
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From: "Joe.C" <yingjoe.chen@mediatek.com>
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Date: Fri, 1 May 2015 15:43:30 +0800
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Subject: [PATCH 43/76] ARM: dts: mt8127: enable basic SMP bringup for mt8127
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Add arch timer node to enable arch-timer support. MT8127 firmware
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doesn't correctly setup arch-timer frequency and CNTVOFF, add
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properties to workaround this.
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This also set cpu enable-method to enable SMP.
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Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
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---
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arch/arm/boot/dts/mt8127.dtsi | 16 ++++++++++++++++
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1 file changed, 16 insertions(+)
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diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
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index aaa7862..7c2090d 100644
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--- a/arch/arm/boot/dts/mt8127.dtsi
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+++ b/arch/arm/boot/dts/mt8127.dtsi
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@@ -23,6 +23,7 @@
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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+ enable-method = "mediatek,mt81xx-tz-smp";
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cpu@0 {
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device_type = "cpu";
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@@ -72,6 +73,21 @@
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};
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};
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+ timer {
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+ compatible = "arm,armv7-timer";
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+ interrupt-parent = <&gic>;
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+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
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+ IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
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+ IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
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+ IRQ_TYPE_LEVEL_LOW)>,
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+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
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+ IRQ_TYPE_LEVEL_LOW)>;
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+ clock-frequency = <13000000>;
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+ arm,cpu-registers-not-fw-configured;
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+ };
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+
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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--
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1.7.10.4
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