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Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
23 lines
906 B
Diff
23 lines
906 B
Diff
From 1d6d5b6d2363cf5a0d175f086209fb208692ec00 Mon Sep 17 00:00:00 2001
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From: Haiying Wang <Haiying.wang@freescale.com>
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Date: Sat, 8 Aug 2015 07:25:02 -0400
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Subject: [PATCH 35/70] arm64/pgtable: add support to map cacheable and non
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shareable memory
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Signed-off-by: Haiying Wang <Haiying.wang@freescale.com>
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---
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arch/arm64/include/asm/pgtable.h | 2 ++
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1 file changed, 2 insertions(+)
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--- a/arch/arm64/include/asm/pgtable.h
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+++ b/arch/arm64/include/asm/pgtable.h
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@@ -392,6 +392,8 @@ static inline int has_transparent_hugepa
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#define pgprot_cached(prot) \
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__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \
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PTE_PXN | PTE_UXN)
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+#define pgprot_cached_ns(prot) \
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+ __pgprot(pgprot_val(pgprot_cached(prot)) ^ PTE_SHARED)
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#define pgprot_device(prot) \
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__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
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#define __HAVE_PHYS_MEM_ACCESS_PROT
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