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95d3d353f8
Copy patches from patches-6.1 to patches-6.6. No changes. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
261 lines
7.4 KiB
Diff
261 lines
7.4 KiB
Diff
From afd36e9d91b0a840983b829a9e95407d8151f7e7 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Sun, 17 Dec 2023 21:49:55 +0000
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Subject: [PATCH 2/4] dt-bindings: clock: mediatek: add clock controllers of
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MT7988
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Add various clock controllers found in the MT7988 SoC to existing
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bindings (if applicable) and add files for the new ethwarp, mcusys
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and xfi-pll clock controllers not previously present in any SoC.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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.../arm/mediatek/mediatek,infracfg.yaml | 1 +
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.../bindings/clock/mediatek,apmixedsys.yaml | 1 +
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.../bindings/clock/mediatek,ethsys.yaml | 1 +
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.../clock/mediatek,mt7988-ethwarp.yaml | 52 +++++++++++++++
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.../clock/mediatek,mt7988-xfi-pll.yaml | 48 ++++++++++++++
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.../bindings/clock/mediatek,topckgen.yaml | 2 +
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.../bindings/net/pcs/mediatek,sgmiisys.yaml | 65 ++++++++++++++++---
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7 files changed, 161 insertions(+), 9 deletions(-)
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create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
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create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
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--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
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@@ -30,6 +30,7 @@ properties:
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- mediatek,mt7629-infracfg
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- mediatek,mt7981-infracfg
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- mediatek,mt7986-infracfg
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+ - mediatek,mt7988-infracfg
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- mediatek,mt8135-infracfg
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- mediatek,mt8167-infracfg
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- mediatek,mt8173-infracfg
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--- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
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+++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
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@@ -22,6 +22,7 @@ properties:
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- mediatek,mt7622-apmixedsys
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- mediatek,mt7981-apmixedsys
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- mediatek,mt7986-apmixedsys
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+ - mediatek,mt7988-apmixedsys
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- mediatek,mt8135-apmixedsys
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- mediatek,mt8173-apmixedsys
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- mediatek,mt8516-apmixedsys
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--- a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
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+++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
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@@ -22,6 +22,7 @@ properties:
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- mediatek,mt7629-ethsys
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- mediatek,mt7981-ethsys
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- mediatek,mt7986-ethsys
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+ - mediatek,mt7988-ethsys
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- const: syscon
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- items:
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- const: mediatek,mt7623-ethsys
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
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@@ -0,0 +1,52 @@
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+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: MediaTek MT7988 ethwarp Controller
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+
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+maintainers:
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+ - Daniel Golle <daniel@makrotopia.org>
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+
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+description:
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+ The Mediatek MT7988 ethwarp controller provides clocks and resets for the
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+ Ethernet related subsystems found the MT7988 SoC.
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+ The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
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+
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+properties:
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+ compatible:
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+ items:
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+ - const: mediatek,mt7988-ethwarp
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+
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+ reg:
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+ maxItems: 1
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+
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+ '#clock-cells':
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+ const: 1
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+
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+ '#reset-cells':
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+ const: 1
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+
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+required:
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+ - compatible
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+ - reg
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+ - '#clock-cells'
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+ - '#reset-cells'
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/reset/ti-syscon.h>
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+ soc {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ clock-controller@15031000 {
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+ compatible = "mediatek,mt7988-ethwarp";
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+ reg = <0 0x15031000 0 0x1000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+ };
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
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@@ -0,0 +1,48 @@
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+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: MediaTek MT7988 XFI PLL Clock Controller
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+
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+maintainers:
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+ - Daniel Golle <daniel@makrotopia.org>
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+
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+description:
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+ The MediaTek XFI PLL controller provides the 156.25MHz clock for the
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+ Ethernet SerDes PHY from the 40MHz top_xtal clock.
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+
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+properties:
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+ compatible:
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+ const: mediatek,mt7988-xfi-pll
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+
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+ reg:
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+ maxItems: 1
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+
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+ resets:
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+ maxItems: 1
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+
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+ '#clock-cells':
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+ const: 1
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+
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+required:
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+ - compatible
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+ - reg
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+ - resets
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+ - '#clock-cells'
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ soc {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ clock-controller@11f40000 {
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+ compatible = "mediatek,mt7988-xfi-pll";
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+ reg = <0 0x11f40000 0 0x1000>;
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+ resets = <&watchdog 16>;
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+ #clock-cells = <1>;
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+ };
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+ };
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--- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
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+++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
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@@ -37,6 +37,8 @@ properties:
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- mediatek,mt7629-topckgen
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- mediatek,mt7981-topckgen
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- mediatek,mt7986-topckgen
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+ - mediatek,mt7988-mcusys
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+ - mediatek,mt7988-topckgen
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- mediatek,mt8167-topckgen
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- mediatek,mt8183-topckgen
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- const: syscon
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--- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
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+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
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@@ -15,15 +15,22 @@ description:
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properties:
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compatible:
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- items:
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- - enum:
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- - mediatek,mt7622-sgmiisys
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- - mediatek,mt7629-sgmiisys
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- - mediatek,mt7981-sgmiisys_0
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- - mediatek,mt7981-sgmiisys_1
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- - mediatek,mt7986-sgmiisys_0
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- - mediatek,mt7986-sgmiisys_1
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- - const: syscon
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+ oneOf:
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+ - items:
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+ - enum:
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+ - mediatek,mt7622-sgmiisys
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+ - mediatek,mt7629-sgmiisys
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+ - mediatek,mt7981-sgmiisys_0
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+ - mediatek,mt7981-sgmiisys_1
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+ - mediatek,mt7986-sgmiisys_0
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+ - mediatek,mt7986-sgmiisys_1
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+ - const: syscon
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+ - items:
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+ - enum:
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+ - mediatek,mt7988-sgmiisys0
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+ - mediatek,mt7988-sgmiisys1
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+ - const: simple-mfd
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+ - const: syscon
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reg:
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maxItems: 1
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@@ -35,11 +42,51 @@ properties:
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description: Invert polarity of the SGMII data lanes
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type: boolean
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+ pcs:
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+ type: object
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+ description: MediaTek LynxI HSGMII PCS
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+ properties:
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+ compatible:
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+ const: mediatek,mt7988-sgmii
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+
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+ clocks:
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+ maxItems: 3
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+
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+ clock-names:
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+ items:
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+ - const: sgmii_sel
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+ - const: sgmii_tx
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+ - const: sgmii_rx
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+
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+ required:
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+ - compatible
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+ - clocks
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+ - clock-names
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+
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+ additionalProperties: false
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+
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required:
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- compatible
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- reg
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- '#clock-cells'
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+allOf:
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+ - if:
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+ properties:
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+ compatible:
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+ contains:
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+ enum:
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+ - mediatek,mt7988-sgmiisys0
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+ - mediatek,mt7988-sgmiisys1
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+
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+ then:
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+ required:
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+ - pcs
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+
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+ else:
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+ properties:
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+ pcs: false
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+
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additionalProperties: false
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examples:
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