mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-25 16:31:13 +00:00
b754b0c721
Removed upstreamed: backport-5.10/850-v5.17-0004-PCI-aardvark-Clear-all-MSIs-at-setup.patch pending-5.10/850-0002-PCI-aardvark-Fix-reading-MSI-interrupt-number.patch All other patches automatically rebased. Build system: x86_64 Build-tested: bcm2711/RPi4B Signed-off-by: John Audia <therealgraysky@proton.me>
49 lines
1.9 KiB
Diff
49 lines
1.9 KiB
Diff
From 13bcdf07cb2ecff5d45d2c141df2539b15211448 Mon Sep 17 00:00:00 2001
|
|
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
|
|
Date: Tue, 30 Nov 2021 18:29:09 +0100
|
|
Subject: [PATCH] PCI: aardvark: Mask all interrupts when unbinding driver
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
Ensure that no interrupt can be triggered after driver unbind.
|
|
|
|
Link: https://lore.kernel.org/r/20211130172913.9727-8-kabel@kernel.org
|
|
Signed-off-by: Pali Rohár <pali@kernel.org>
|
|
Signed-off-by: Marek Behún <kabel@kernel.org>
|
|
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
|
---
|
|
drivers/pci/controller/pci-aardvark.c | 21 +++++++++++++++++++++
|
|
1 file changed, 21 insertions(+)
|
|
|
|
--- a/drivers/pci/controller/pci-aardvark.c
|
|
+++ b/drivers/pci/controller/pci-aardvark.c
|
|
@@ -1704,6 +1704,27 @@ static int advk_pcie_remove(struct platf
|
|
val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
|
advk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG);
|
|
|
|
+ /* Disable MSI */
|
|
+ val = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
|
|
+ val &= ~PCIE_CORE_CTRL2_MSI_ENABLE;
|
|
+ advk_writel(pcie, val, PCIE_CORE_CTRL2_REG);
|
|
+
|
|
+ /* Clear MSI address */
|
|
+ advk_writel(pcie, 0, PCIE_MSI_ADDR_LOW_REG);
|
|
+ advk_writel(pcie, 0, PCIE_MSI_ADDR_HIGH_REG);
|
|
+
|
|
+ /* Mask all interrupts */
|
|
+ advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
|
|
+ advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);
|
|
+ advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
|
|
+ advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_MASK_REG);
|
|
+
|
|
+ /* Clear all interrupts */
|
|
+ advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
|
|
+ advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
|
|
+ advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
|
|
+ advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
|
|
+
|
|
/* Remove IRQ domains */
|
|
advk_pcie_remove_msi_irq_domain(pcie);
|
|
advk_pcie_remove_irq_domain(pcie);
|