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L2 learning on the CPU port is currently not consistently configured and relies on the default configuration of the device. On RTL83xx, it is disabled for packets transmitted with a TX header, as hardware learning corrupts the forwarding table otherwise. As a result, unneeded flooding of traffic for the CPU port can already happen on some devices now. It is also likely that similar issues exist on RTL93xx, which doesn't have a field to disable learning in the TX header. To address this, disable hardware learning for the CPU port globally on all devices. Instead, enable assisted learning to let DSA write FDB entries to the switch. For now, this does not sync local/bridge entries to the switch. However, support for that was added in Linux 5.14, so the next switch to a newer kernel version is going to fix this. Signed-off-by: Jan Hoffmann <jan@3e8.eu> |
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| .. | ||
| base-files | ||
| dts-5.10 | ||
| files/firmware/rtl838x_phy | ||
| files-5.10 | ||
| image | ||
| patches-5.10 | ||
| profiles | ||
| rtl838x | ||
| rtl839x | ||
| rtl930x | ||
| rtl931x | ||
| Makefile | ||