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338f40b3b4
Add all essential MTK SDHC properties to support the new mmc-mtk
driver. Since this driver relies on power regulators, we also
need to enable this feature for MT7620, just like MT762{1,8}.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Co-authored-by: John Thomson <git@johnthomson.fastmail.com.au>
527 lines
8.6 KiB
Plaintext
527 lines
8.6 KiB
Plaintext
/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mediatek,mt7628an-soc";
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aliases {
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serial0 = &uartlite;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mips,mips24KEc";
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reg = <0>;
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};
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};
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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cpuintc: cpuintc {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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mmc_clk: mmc-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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clock-accuracy = <100>;
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};
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mmc_reg_1v8: regulator-1v8 {
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compatible = "regulator-fixed";
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enable-active-high;
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regulator-always-on;
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regulator-max-microvolt = <1800000>;
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regulator-min-microvolt = <1800000>;
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regulator-name = "mmc_io";
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};
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mmc_reg_3v3: regulator-3v3 {
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compatible = "regulator-fixed";
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enable-active-high;
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regulator-always-on;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "mmc_power";
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};
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palmbus: palmbus@10000000 {
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compatible = "palmbus";
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reg = <0x10000000 0x200000>;
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ranges = <0x0 0x10000000 0x1FFFFF>;
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#address-cells = <1>;
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#size-cells = <1>;
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sysc: syscon@0 {
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compatible = "ralink,mt7628-sysc", "ralink,mt7688-sysc", "syscon";
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reg = <0x0 0x100>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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watchdog: watchdog@100 {
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compatible = "mediatek,mt7621-wdt";
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reg = <0x100 0x100>;
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mediatek,sysctl = <&sysc>;
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};
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intc: intc@200 {
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compatible = "ralink,rt2880-intc";
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reg = <0x200 0x100>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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ralink,intc-registers = <0x9c 0xa0
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0x6c 0xa4
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0x80 0x78>;
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};
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memc: memc@300 {
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compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
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reg = <0x300 0x100>;
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interrupt-parent = <&intc>;
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interrupts = <3>;
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};
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gpio: gpio@600 {
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compatible = "mediatek,mt7621-gpio";
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reg = <0x600 0x100>;
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interrupt-parent = <&intc>;
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interrupts = <6>;
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#interrupt-cells = <2>;
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interrupt-controller;
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gpio-controller;
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#gpio-cells = <2>;
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};
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i2c: i2c@900 {
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compatible = "mediatek,mt7621-i2c";
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reg = <0x900 0x100>;
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clocks = <&sysc 7>;
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clock-names = "i2c";
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resets = <&sysc 16>;
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reset-names = "i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c_pins>;
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};
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i2s: i2s@a00 {
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compatible = "mediatek,mt7628-i2s";
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reg = <0xa00 0x100>;
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clocks = <&sysc 8>;
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resets = <&sysc 17>;
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reset-names = "i2s";
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interrupt-parent = <&intc>;
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interrupts = <10>;
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txdma-req = <2>;
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rxdma-req = <3>;
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dmas = <&gdma 4>,
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<&gdma 6>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi0: spi@b00 {
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compatible = "ralink,mt7621-spi";
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reg = <0xb00 0x100>;
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clocks = <&sysc 9>;
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clock-names = "spi";
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resets = <&sysc 18>;
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reset-names = "spi";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins>;
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status = "disabled";
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};
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uartlite: uart0@c00 {
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compatible = "ns16550a";
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reg = <0xc00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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no-loopback-test;
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clocks = <&sysc 11>;
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resets = <&sysc 12>;
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interrupt-parent = <&intc>;
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interrupts = <20>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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};
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uart1: uart1@d00 {
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compatible = "ns16550a";
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reg = <0xd00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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no-loopback-test;
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clocks = <&sysc 12>;
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resets = <&sysc 19>;
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interrupt-parent = <&intc>;
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interrupts = <21>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "disabled";
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};
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uart2: uart2@e00 {
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compatible = "ns16550a";
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reg = <0xe00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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no-loopback-test;
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clocks = <&sysc 13>;
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resets = <&sysc 20>;
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interrupt-parent = <&intc>;
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interrupts = <22>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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status = "disabled";
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};
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pwm: pwm@5000 {
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compatible = "mediatek,mt7628-pwm";
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reg = <0x5000 0x1000>;
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#pwm-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
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status = "disabled";
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};
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pcm: pcm@2000 {
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compatible = "ralink,mt7620a-pcm";
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reg = <0x2000 0x800>;
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resets = <&sysc 11>;
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reset-names = "pcm";
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interrupt-parent = <&intc>;
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interrupts = <4>;
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status = "disabled";
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};
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gdma: gdma@2800 {
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compatible = "ralink,rt3883-gdma";
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reg = <0x2800 0x800>;
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resets = <&sysc 14>;
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reset-names = "dma";
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interrupt-parent = <&intc>;
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interrupts = <7>;
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#dma-cells = <1>;
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#dma-channels = <16>;
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#dma-requests = <16>;
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status = "disabled";
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};
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};
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pinctrl: pinctrl {
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compatible = "ralink,rt2880-pinmux";
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinctrl0 {
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};
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spi_pins: spi_pins {
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spi_pins {
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groups = "spi";
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function = "spi";
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};
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};
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spi_cs1_pins: spi_cs1 {
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spi_cs1 {
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groups = "spi cs1";
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function = "spi cs1";
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};
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};
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i2c_pins: i2c_pins {
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i2c_pins {
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groups = "i2c";
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function = "i2c";
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};
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};
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i2s_pins: i2s {
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i2s {
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groups = "i2s";
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function = "i2s";
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};
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};
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uart0_pins: uartlite {
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uartlite {
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groups = "uart0";
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function = "uart0";
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};
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};
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uart1_pins: uart1 {
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uart1 {
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groups = "uart1";
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function = "uart1";
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};
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};
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uart2_pins: uart2 {
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uart2 {
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groups = "uart2";
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function = "uart2";
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};
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};
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sdxc_pins: sdxc {
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sdxc {
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groups = "sdmode";
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function = "sdxc";
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};
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};
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pwm0_pins: pwm0 {
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pwm0 {
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groups = "pwm0";
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function = "pwm0";
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};
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};
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pwm1_pins: pwm1 {
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pwm1 {
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groups = "pwm1";
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function = "pwm1";
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};
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};
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pcm_i2s_pins: pcm_i2s {
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pcm_i2s {
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groups = "i2s";
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function = "pcm";
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};
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};
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refclk_pins: refclk {
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refclk {
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groups = "refclk";
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function = "refclk";
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};
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};
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};
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usbphy: usbphy@10120000 {
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compatible = "mediatek,mt7628-usbphy", "mediatek,mt7620-usbphy";
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reg = <0x10120000 0x1000>;
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#phy-cells = <0>;
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ralink,sysctl = <&sysc>;
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/* usb phy reset is only controled by RSTCTRL bit 22 */
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resets = <&sysc 22>, <&sysc 25>;
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reset-names = "host", "device";
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};
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sdhci: mmc@10130000 {
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compatible = "mediatek,mt7620-mmc", "ralink,mt7620-sdhci";
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reg = <0x10130000 0x4000>;
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bus-width = <4>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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clocks = <&mmc_clk>, <&mmc_clk>;
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clock-names = "source", "hclk";
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disable-wp;
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interrupt-parent = <&intc>;
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interrupts = <14>;
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max-frequency = <48000000>;
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&sdxc_pins>;
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pinctrl-1 = <&sdxc_pins>;
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resets = <&sysc 30>;
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reset-names = "hrst";
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vmmc-supply = <&mmc_reg_3v3>;
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vqmmc-supply = <&mmc_reg_1v8>;
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status = "disabled";
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};
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ehci: ehci@101c0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "generic-ehci";
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reg = <0x101c0000 0x1000>;
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phys = <&usbphy>;
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phy-names = "usb";
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interrupt-parent = <&intc>;
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interrupts = <18>;
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ehci_port1: port@1 {
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reg = <1>;
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#trigger-source-cells = <0>;
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};
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};
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ohci: ohci@101c1000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "generic-ohci";
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reg = <0x101c1000 0x1000>;
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phys = <&usbphy>;
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phy-names = "usb";
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interrupt-parent = <&intc>;
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interrupts = <18>;
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ohci_port1: port@1 {
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reg = <1>;
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#trigger-source-cells = <0>;
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};
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};
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ethernet: ethernet@10100000 {
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compatible = "ralink,rt5350-eth";
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reg = <0x10100000 0x10000>;
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interrupt-parent = <&cpuintc>;
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interrupts = <5>;
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resets = <&sysc 21>, <&sysc 23>;
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reset-names = "fe", "esw";
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mediatek,switch = <&esw>;
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};
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esw: esw@10110000 {
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compatible = "ralink,rt3050-esw";
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reg = <0x10110000 0x8000>;
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resets = <&sysc 24>;
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reset-names = "ephy";
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interrupt-parent = <&intc>;
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interrupts = <17>;
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};
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pcie: pcie@10140000 {
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compatible = "mediatek,mt7620-pci";
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reg = <0x10140000 0x100
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0x10142000 0x100>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-parent = <&cpuintc>;
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interrupts = <4>;
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resets = <&sysc 26>;
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reset-names = "pcie0";
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status = "disabled";
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device_type = "pci";
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bus-range = <0 255>;
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ranges = <
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0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
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0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
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>;
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pcie0: pcie@0,0 {
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reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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};
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};
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wmac: wmac@10300000 {
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compatible = "mediatek,mt7628-wmac";
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reg = <0x10300000 0x100000>;
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clocks = <&sysc 14>;
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interrupt-parent = <&cpuintc>;
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interrupts = <6>;
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status = "disabled";
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};
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};
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