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511 lines
15 KiB
Diff
511 lines
15 KiB
Diff
From 6fe2927863de96edf35d8357712dbf83a489f556 Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Thu, 19 Nov 2020 17:43:12 +0200
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Subject: [PATCH 106/247] clk: at91: clk-sam9x60-pll: allow runtime changes for
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pll
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Allow runtime frequency changes for PLLs registered with proper flags.
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This is necessary for CPU PLL on SAMA7G5 which is used by DVFS.
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Link: https://lore.kernel.org/r/1605800597-16720-7-git-send-email-claudiu.beznea@microchip.com
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/at91/clk-sam9x60-pll.c | 145 +++++++++++++++++++++++++----
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drivers/clk/at91/pmc.h | 4 +-
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drivers/clk/at91/sam9x60.c | 22 ++++-
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drivers/clk/at91/sama7g5.c | 67 +++++++++----
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4 files changed, 197 insertions(+), 41 deletions(-)
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--- a/drivers/clk/at91/clk-sam9x60-pll.c
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+++ b/drivers/clk/at91/clk-sam9x60-pll.c
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@@ -229,6 +229,57 @@ static int sam9x60_frac_pll_set_rate(str
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return sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);
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}
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+static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
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+ unsigned long parent_rate)
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+{
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+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
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+ struct sam9x60_frac *frac = to_sam9x60_frac(core);
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+ struct regmap *regmap = core->regmap;
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+ unsigned long irqflags;
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+ unsigned int val, cfrac, cmul;
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+ long ret;
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+
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+ ret = sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);
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+ if (ret <= 0)
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+ return ret;
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+
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+ spin_lock_irqsave(core->lock, irqflags);
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+
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+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
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+ core->id);
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+ regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
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+ cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
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+ cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
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+
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+ if (cmul == frac->mul && cfrac == frac->frac)
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+ goto unlock;
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+
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+ regmap_write(regmap, AT91_PMC_PLL_CTRL1,
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+ (frac->mul << core->layout->mul_shift) |
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+ (frac->frac << core->layout->frac_shift));
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+
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+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
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+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
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+ AT91_PMC_PLL_UPDT_UPDATE | core->id);
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+
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+ regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
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+ AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
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+ AT91_PMC_PLL_CTRL0_ENLOCK |
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+ AT91_PMC_PLL_CTRL0_ENPLL);
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+
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+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
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+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
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+ AT91_PMC_PLL_UPDT_UPDATE | core->id);
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+
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+ while (!sam9x60_pll_ready(regmap, core->id))
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+ cpu_relax();
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+
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+unlock:
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+ spin_unlock_irqrestore(core->lock, irqflags);
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+
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+ return ret;
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+}
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+
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static const struct clk_ops sam9x60_frac_pll_ops = {
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.prepare = sam9x60_frac_pll_prepare,
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.unprepare = sam9x60_frac_pll_unprepare,
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@@ -238,6 +289,15 @@ static const struct clk_ops sam9x60_frac
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.set_rate = sam9x60_frac_pll_set_rate,
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};
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+static const struct clk_ops sam9x60_frac_pll_ops_chg = {
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+ .prepare = sam9x60_frac_pll_prepare,
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+ .unprepare = sam9x60_frac_pll_unprepare,
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+ .is_prepared = sam9x60_frac_pll_is_prepared,
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+ .recalc_rate = sam9x60_frac_pll_recalc_rate,
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+ .round_rate = sam9x60_frac_pll_round_rate,
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+ .set_rate = sam9x60_frac_pll_set_rate_chg,
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+};
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+
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static int sam9x60_div_pll_prepare(struct clk_hw *hw)
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{
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struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
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@@ -384,6 +444,44 @@ static int sam9x60_div_pll_set_rate(stru
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return 0;
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}
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+static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
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+ unsigned long parent_rate)
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+{
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+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
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+ struct sam9x60_div *div = to_sam9x60_div(core);
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+ struct regmap *regmap = core->regmap;
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+ unsigned long irqflags;
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+ unsigned int val, cdiv;
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+
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+ div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
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+
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+ spin_lock_irqsave(core->lock, irqflags);
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+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
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+ core->id);
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+ regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
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+ cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
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+
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+ /* Stop if nothing changed. */
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+ if (cdiv == div->div)
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+ goto unlock;
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+
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+ regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
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+ core->layout->div_mask,
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+ (div->div << core->layout->div_shift));
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+
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+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
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+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
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+ AT91_PMC_PLL_UPDT_UPDATE | core->id);
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+
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+ while (!sam9x60_pll_ready(regmap, core->id))
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+ cpu_relax();
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+
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+unlock:
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+ spin_unlock_irqrestore(core->lock, irqflags);
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+
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+ return 0;
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+}
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+
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static const struct clk_ops sam9x60_div_pll_ops = {
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.prepare = sam9x60_div_pll_prepare,
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.unprepare = sam9x60_div_pll_unprepare,
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@@ -393,17 +491,26 @@ static const struct clk_ops sam9x60_div_
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.set_rate = sam9x60_div_pll_set_rate,
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};
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+static const struct clk_ops sam9x60_div_pll_ops_chg = {
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+ .prepare = sam9x60_div_pll_prepare,
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+ .unprepare = sam9x60_div_pll_unprepare,
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+ .is_prepared = sam9x60_div_pll_is_prepared,
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+ .recalc_rate = sam9x60_div_pll_recalc_rate,
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+ .round_rate = sam9x60_div_pll_round_rate,
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+ .set_rate = sam9x60_div_pll_set_rate_chg,
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+};
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+
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struct clk_hw * __init
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sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
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const char *name, const char *parent_name,
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struct clk_hw *parent_hw, u8 id,
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const struct clk_pll_characteristics *characteristics,
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- const struct clk_pll_layout *layout, bool critical)
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+ const struct clk_pll_layout *layout, u32 flags)
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{
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struct sam9x60_frac *frac;
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struct clk_hw *hw;
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struct clk_init_data init;
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- unsigned long parent_rate, flags;
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+ unsigned long parent_rate, irqflags;
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unsigned int val;
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int ret;
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@@ -417,10 +524,12 @@ sam9x60_clk_register_frac_pll(struct reg
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init.name = name;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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- init.ops = &sam9x60_frac_pll_ops;
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- init.flags = CLK_SET_RATE_GATE;
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- if (critical)
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- init.flags |= CLK_IS_CRITICAL;
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+ if (flags & CLK_SET_RATE_GATE)
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+ init.ops = &sam9x60_frac_pll_ops;
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+ else
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+ init.ops = &sam9x60_frac_pll_ops_chg;
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+
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+ init.flags = flags;
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frac->core.id = id;
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frac->core.hw.init = &init;
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@@ -429,7 +538,7 @@ sam9x60_clk_register_frac_pll(struct reg
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frac->core.regmap = regmap;
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frac->core.lock = lock;
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- spin_lock_irqsave(frac->core.lock, flags);
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+ spin_lock_irqsave(frac->core.lock, irqflags);
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if (sam9x60_pll_ready(regmap, id)) {
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regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
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AT91_PMC_PLL_UPDT_ID_MSK, id);
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@@ -457,7 +566,7 @@ sam9x60_clk_register_frac_pll(struct reg
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goto free;
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}
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}
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- spin_unlock_irqrestore(frac->core.lock, flags);
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+ spin_unlock_irqrestore(frac->core.lock, irqflags);
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hw = &frac->core.hw;
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ret = clk_hw_register(NULL, hw);
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@@ -469,7 +578,7 @@ sam9x60_clk_register_frac_pll(struct reg
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return hw;
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free:
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- spin_unlock_irqrestore(frac->core.lock, flags);
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+ spin_unlock_irqrestore(frac->core.lock, irqflags);
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kfree(frac);
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return hw;
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}
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@@ -478,12 +587,12 @@ struct clk_hw * __init
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sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
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const char *name, const char *parent_name, u8 id,
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const struct clk_pll_characteristics *characteristics,
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- const struct clk_pll_layout *layout, bool critical)
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+ const struct clk_pll_layout *layout, u32 flags)
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{
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struct sam9x60_div *div;
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struct clk_hw *hw;
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struct clk_init_data init;
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- unsigned long flags;
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+ unsigned long irqflags;
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unsigned int val;
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int ret;
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@@ -497,11 +606,11 @@ sam9x60_clk_register_div_pll(struct regm
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init.name = name;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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- init.ops = &sam9x60_div_pll_ops;
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- init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
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- CLK_SET_RATE_PARENT;
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- if (critical)
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- init.flags |= CLK_IS_CRITICAL;
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+ if (flags & CLK_SET_RATE_GATE)
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+ init.ops = &sam9x60_div_pll_ops;
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+ else
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+ init.ops = &sam9x60_div_pll_ops_chg;
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+ init.flags = flags;
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div->core.id = id;
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div->core.hw.init = &init;
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@@ -510,14 +619,14 @@ sam9x60_clk_register_div_pll(struct regm
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div->core.regmap = regmap;
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div->core.lock = lock;
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- spin_lock_irqsave(div->core.lock, flags);
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+ spin_lock_irqsave(div->core.lock, irqflags);
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regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
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AT91_PMC_PLL_UPDT_ID_MSK, id);
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regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
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div->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val);
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- spin_unlock_irqrestore(div->core.lock, flags);
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+ spin_unlock_irqrestore(div->core.lock, irqflags);
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hw = &div->core.hw;
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ret = clk_hw_register(NULL, hw);
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--- a/drivers/clk/at91/pmc.h
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+++ b/drivers/clk/at91/pmc.h
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@@ -190,14 +190,14 @@ struct clk_hw * __init
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sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
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const char *name, const char *parent_name, u8 id,
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const struct clk_pll_characteristics *characteristics,
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- const struct clk_pll_layout *layout, bool critical);
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+ const struct clk_pll_layout *layout, u32 flags);
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struct clk_hw * __init
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sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
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const char *name, const char *parent_name,
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struct clk_hw *parent_hw, u8 id,
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const struct clk_pll_characteristics *characteristics,
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- const struct clk_pll_layout *layout, bool critical);
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+ const struct clk_pll_layout *layout, u32 flags);
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struct clk_hw * __init
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at91_clk_register_programmable(struct regmap *regmap, const char *name,
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--- a/drivers/clk/at91/sam9x60.c
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+++ b/drivers/clk/at91/sam9x60.c
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@@ -224,13 +224,24 @@ static void __init sam9x60_pmc_setup(str
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hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck",
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"mainck", sam9x60_pmc->chws[PMC_MAIN],
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0, &plla_characteristics,
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- &pll_frac_layout, true);
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+ &pll_frac_layout,
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+ /*
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+ * This feeds pllack_divck which
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+ * feeds CPU. It should not be
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+ * disabled.
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+ */
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+ CLK_IS_CRITICAL | CLK_SET_RATE_GATE);
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if (IS_ERR(hw))
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goto err_free;
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hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck",
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"pllack_fracck", 0, &plla_characteristics,
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- &pll_div_layout, true);
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+ &pll_div_layout,
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+ /*
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+ * This feeds CPU. It should not
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+ * be disabled.
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+ */
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+ CLK_IS_CRITICAL | CLK_SET_RATE_GATE);
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if (IS_ERR(hw))
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goto err_free;
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@@ -239,13 +250,16 @@ static void __init sam9x60_pmc_setup(str
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hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck",
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"main_osc", main_osc_hw, 1,
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&upll_characteristics,
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- &pll_frac_layout, false);
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+ &pll_frac_layout, CLK_SET_RATE_GATE);
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if (IS_ERR(hw))
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goto err_free;
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hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck",
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"upllck_fracck", 1, &upll_characteristics,
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- &pll_div_layout, false);
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+ &pll_div_layout,
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+ CLK_SET_RATE_GATE |
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+ CLK_SET_PARENT_GATE |
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+ CLK_SET_RATE_PARENT);
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if (IS_ERR(hw))
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goto err_free;
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--- a/drivers/clk/at91/sama7g5.c
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+++ b/drivers/clk/at91/sama7g5.c
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@@ -95,15 +95,15 @@ static const struct clk_pll_layout pll_l
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* @p: clock parent
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* @l: clock layout
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* @t: clock type
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- * @f: true if clock is critical and cannot be disabled
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+ * @f: clock flags
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* @eid: export index in sama7g5->chws[] array
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*/
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static const struct {
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const char *n;
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const char *p;
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const struct clk_pll_layout *l;
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+ unsigned long f;
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u8 t;
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- u8 c;
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u8 eid;
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} sama7g5_plls[][PLL_ID_MAX] = {
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[PLL_ID_CPU] = {
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@@ -111,13 +111,18 @@ static const struct {
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.p = "mainck",
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.l = &pll_layout_frac,
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.t = PLL_TYPE_FRAC,
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- .c = 1, },
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+ /*
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+ * This feeds cpupll_divpmcck which feeds CPU. It should
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+ * not be disabled.
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+ */
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+ .f = CLK_IS_CRITICAL, },
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{ .n = "cpupll_divpmcck",
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.p = "cpupll_fracck",
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.l = &pll_layout_divpmc,
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.t = PLL_TYPE_DIV,
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- .c = 1,
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+ /* This feeds CPU. It should not be disabled. */
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+ .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
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.eid = PMC_CPUPLL, },
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},
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@@ -126,13 +131,22 @@ static const struct {
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.p = "mainck",
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.l = &pll_layout_frac,
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.t = PLL_TYPE_FRAC,
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- .c = 1, },
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+ /*
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+ * This feeds syspll_divpmcck which may feed critial parts
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+ * of the systems like timers. Therefore it should not be
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+ * disabled.
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+ */
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+ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
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{ .n = "syspll_divpmcck",
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.p = "syspll_fracck",
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.l = &pll_layout_divpmc,
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.t = PLL_TYPE_DIV,
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- .c = 1,
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+ /*
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+ * This may feed critial parts of the systems like timers.
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+ * Therefore it should not be disabled.
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+ */
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+ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
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.eid = PMC_SYSPLL, },
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},
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@@ -141,55 +155,71 @@ static const struct {
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.p = "mainck",
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.l = &pll_layout_frac,
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.t = PLL_TYPE_FRAC,
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- .c = 1, },
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+ /*
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+ * This feeds ddrpll_divpmcck which feeds DDR. It should not
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+ * be disabled.
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+ */
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+ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
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{ .n = "ddrpll_divpmcck",
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.p = "ddrpll_fracck",
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.l = &pll_layout_divpmc,
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.t = PLL_TYPE_DIV,
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- .c = 1, },
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+ /* This feeds DDR. It should not be disabled. */
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+ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
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},
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[PLL_ID_IMG] = {
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{ .n = "imgpll_fracck",
|
|
.p = "mainck",
|
|
.l = &pll_layout_frac,
|
|
- .t = PLL_TYPE_FRAC, },
|
|
+ .t = PLL_TYPE_FRAC,
|
|
+ .f = CLK_SET_RATE_GATE, },
|
|
|
|
{ .n = "imgpll_divpmcck",
|
|
.p = "imgpll_fracck",
|
|
.l = &pll_layout_divpmc,
|
|
- .t = PLL_TYPE_DIV, },
|
|
+ .t = PLL_TYPE_DIV,
|
|
+ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
|
|
+ CLK_SET_RATE_PARENT, },
|
|
},
|
|
|
|
[PLL_ID_BAUD] = {
|
|
{ .n = "baudpll_fracck",
|
|
.p = "mainck",
|
|
.l = &pll_layout_frac,
|
|
- .t = PLL_TYPE_FRAC, },
|
|
+ .t = PLL_TYPE_FRAC,
|
|
+ .f = CLK_SET_RATE_GATE, },
|
|
|
|
{ .n = "baudpll_divpmcck",
|
|
.p = "baudpll_fracck",
|
|
.l = &pll_layout_divpmc,
|
|
- .t = PLL_TYPE_DIV, },
|
|
+ .t = PLL_TYPE_DIV,
|
|
+ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
|
|
+ CLK_SET_RATE_PARENT, },
|
|
},
|
|
|
|
[PLL_ID_AUDIO] = {
|
|
{ .n = "audiopll_fracck",
|
|
.p = "main_xtal",
|
|
.l = &pll_layout_frac,
|
|
- .t = PLL_TYPE_FRAC, },
|
|
+ .t = PLL_TYPE_FRAC,
|
|
+ .f = CLK_SET_RATE_GATE, },
|
|
|
|
{ .n = "audiopll_divpmcck",
|
|
.p = "audiopll_fracck",
|
|
.l = &pll_layout_divpmc,
|
|
.t = PLL_TYPE_DIV,
|
|
+ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
|
|
+ CLK_SET_RATE_PARENT,
|
|
.eid = PMC_AUDIOPMCPLL, },
|
|
|
|
{ .n = "audiopll_diviock",
|
|
.p = "audiopll_fracck",
|
|
.l = &pll_layout_divio,
|
|
.t = PLL_TYPE_DIV,
|
|
+ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
|
|
+ CLK_SET_RATE_PARENT,
|
|
.eid = PMC_AUDIOIOPLL, },
|
|
},
|
|
|
|
@@ -197,12 +227,15 @@ static const struct {
|
|
{ .n = "ethpll_fracck",
|
|
.p = "main_xtal",
|
|
.l = &pll_layout_frac,
|
|
- .t = PLL_TYPE_FRAC, },
|
|
+ .t = PLL_TYPE_FRAC,
|
|
+ .f = CLK_SET_RATE_GATE, },
|
|
|
|
{ .n = "ethpll_divpmcck",
|
|
.p = "ethpll_fracck",
|
|
.l = &pll_layout_divpmc,
|
|
- .t = PLL_TYPE_DIV, },
|
|
+ .t = PLL_TYPE_DIV,
|
|
+ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
|
|
+ CLK_SET_RATE_PARENT, },
|
|
},
|
|
};
|
|
|
|
@@ -890,7 +923,7 @@ static void __init sama7g5_pmc_setup(str
|
|
sama7g5_plls[i][j].p, parent_hw, i,
|
|
&pll_characteristics,
|
|
sama7g5_plls[i][j].l,
|
|
- sama7g5_plls[i][j].c);
|
|
+ sama7g5_plls[i][j].f);
|
|
break;
|
|
|
|
case PLL_TYPE_DIV:
|
|
@@ -899,7 +932,7 @@ static void __init sama7g5_pmc_setup(str
|
|
sama7g5_plls[i][j].p, i,
|
|
&pll_characteristics,
|
|
sama7g5_plls[i][j].l,
|
|
- sama7g5_plls[i][j].c);
|
|
+ sama7g5_plls[i][j].f);
|
|
break;
|
|
|
|
default:
|