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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
80 lines
2.2 KiB
Diff
80 lines
2.2 KiB
Diff
From ff35d239b7b64f71d7dd9d0ce887647de2cacfcc Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sun, 15 May 2022 23:00:46 +0200
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Subject: [PATCH] clk: qcom: ipq8074: add USB GDSCs
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Add GDSC-s for each of the two USB controllers built-in the IPQ8074.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20220515210048.483898-9-robimarko@gmail.com
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---
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drivers/clk/qcom/Kconfig | 1 +
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drivers/clk/qcom/gcc-ipq8074.c | 24 ++++++++++++++++++++++++
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2 files changed, 25 insertions(+)
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--- a/drivers/clk/qcom/Kconfig
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+++ b/drivers/clk/qcom/Kconfig
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@@ -166,6 +166,7 @@ config IPQ_LCC_806X
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config IPQ_GCC_8074
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tristate "IPQ8074 Global Clock Controller"
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+ select QCOM_GDSC
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help
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Support for global clock controller on ipq8074 devices.
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Say Y if you want to use peripheral devices such as UART, SPI,
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -22,6 +22,7 @@
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#include "clk-alpha-pll.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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+#include "gdsc.h"
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#include "reset.h"
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enum {
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@@ -4408,6 +4409,22 @@ static struct clk_branch gcc_pcie0_axi_s
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},
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};
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+static struct gdsc usb0_gdsc = {
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+ .gdscr = 0x3e078,
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+ .pd = {
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+ .name = "usb0_gdsc",
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+ },
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+ .pwrsts = PWRSTS_OFF_ON,
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+};
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+
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+static struct gdsc usb1_gdsc = {
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+ .gdscr = 0x3f078,
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+ .pd = {
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+ .name = "usb1_gdsc",
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+ },
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+ .pwrsts = PWRSTS_OFF_ON,
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+};
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+
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static const struct alpha_pll_config ubi32_pll_config = {
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.l = 0x4e,
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.config_ctl_val = 0x200d4aa8,
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@@ -4811,6 +4828,11 @@ static const struct qcom_reset_map gcc_i
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[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
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};
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+static struct gdsc *gcc_ipq8074_gdscs[] = {
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+ [USB0_GDSC] = &usb0_gdsc,
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+ [USB1_GDSC] = &usb1_gdsc,
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+};
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+
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static const struct of_device_id gcc_ipq8074_match_table[] = {
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{ .compatible = "qcom,gcc-ipq8074" },
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{ }
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@@ -4833,6 +4855,8 @@ static const struct qcom_cc_desc gcc_ipq
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.num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
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.clk_hws = gcc_ipq8074_hws,
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.num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
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+ .gdscs = gcc_ipq8074_gdscs,
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+ .num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs),
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};
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static int gcc_ipq8074_probe(struct platform_device *pdev)
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