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f577cb25c0
The following patches were dropped because they are already applied
upstream:
- 0038-MIPS-lantiq-fpi-on-ar9.patch
- 0039-MIPS-lantiq-initialize-usb-on-boot.patch
- 0042-USB-DWC2-big-endian-support.patch
- 0043-gpio-stp-xway-fix-phy-mask.patch
All other patches were simply refreshed, except the following:
- 0001-MIPS-lantiq-add-pcie-driver.patch
Changes to arch/mips/lantiq/xway/sysctrl.c (these changes disabled
some PMU gates for the vrx200 / VR9 SoCs) were removed since the
upstream kernel disables unused PMU gates automatically (since
95135bfa7ead1becc2879230f72583dde2b71a0c
"MIPS: Lantiq: Deactivate most of the devices by default").
- 0025-NET-MIPS-lantiq-adds-xrx200-net.patch
Since OpenWrt commit 55ba20afcc drivers
should use of_get_mac_address(). of_get_mac_address_mtd is not
available for drivers anymore since it's called automatically within
of_get_mac_address().
- 0028-NET-lantiq-various-etop-fixes.patch
Same changes as in 0025-NET-MIPS-lantiq-adds-xrx200-net.patch
While refreshing the kernel configuration SPI support had to be moved to
config-4.4 because otherwise M25P80 was disabled.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48307
42 lines
1.3 KiB
Diff
42 lines
1.3 KiB
Diff
From 76e153079f02d26e3357302d2886a0c8aaaec64d Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sun, 28 Jul 2013 18:02:06 +0200
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Subject: [PATCH 15/36] MTD: lantiq: xway: remove endless loop
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The reset loop logic could run into a endless loop. Lets fix it as requested.
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--> http://lists.infradead.org/pipermail/linux-mtd/2012-September/044240.html
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/mtd/nand/xway_nand.c | 10 ++++++++--
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1 file changed, 8 insertions(+), 2 deletions(-)
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--- a/drivers/mtd/nand/xway_nand.c
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+++ b/drivers/mtd/nand/xway_nand.c
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@@ -59,16 +59,22 @@ static u32 xway_latchcmd;
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static void xway_reset_chip(struct nand_chip *chip)
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{
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unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
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+ unsigned long timeout;
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unsigned long flags;
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nandaddr &= ~NAND_WRITE_ADDR;
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nandaddr |= NAND_WRITE_CMD;
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/* finish with a reset */
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+ timeout = jiffies + msecs_to_jiffies(20);
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+
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spin_lock_irqsave(&ebu_lock, flags);
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writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr);
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- while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
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- ;
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+ do {
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+ if ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
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+ break;
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+ cond_resched();
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+ } while (!time_after_eq(jiffies, timeout));
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spin_unlock_irqrestore(&ebu_lock, flags);
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}
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