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c09eb08dad
Import pending patches to support the upcoming Filogic platforms. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
100 lines
2.7 KiB
Diff
100 lines
2.7 KiB
Diff
From 4569ef02981f20b236a8cdc3a57b4d27fbdbc22e Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 27 Jul 2022 11:01:34 +0800
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Subject: [PATCH 13/31] pwm: mtk: add support for MediaTek MT7981 SoC
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This patch adds PWM support for MediaTek MT7981 SoC.
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MT7981 uses a different register offset so we have to add a version field
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to indicate the IP core version.
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Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/pwm/pwm-mtk.c | 34 ++++++++++++++++++++++++++++++++--
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1 file changed, 32 insertions(+), 2 deletions(-)
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--- a/drivers/pwm/pwm-mtk.c
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+++ b/drivers/pwm/pwm-mtk.c
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@@ -29,13 +29,23 @@
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#define NSEC_PER_SEC 1000000000L
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-static const unsigned int mtk_pwm_reg_offset[] = {
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+enum mtk_pwm_reg_ver {
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+ PWM_REG_V1,
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+ PWM_REG_V2,
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+};
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+
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+static const unsigned int mtk_pwm_reg_offset_v1[] = {
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0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
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};
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+static const unsigned int mtk_pwm_reg_offset_v2[] = {
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+ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
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+};
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+
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struct mtk_pwm_soc {
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unsigned int num_pwms;
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bool pwm45_fixup;
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+ enum mtk_pwm_reg_ver reg_ver;
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};
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struct mtk_pwm_priv {
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@@ -49,7 +59,16 @@ struct mtk_pwm_priv {
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static void mtk_pwm_w32(struct udevice *dev, uint channel, uint reg, uint val)
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{
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struct mtk_pwm_priv *priv = dev_get_priv(dev);
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- u32 offset = mtk_pwm_reg_offset[channel];
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+ u32 offset;
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+
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+ switch (priv->soc->reg_ver) {
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+ case PWM_REG_V2:
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+ offset = mtk_pwm_reg_offset_v2[channel];
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+ break;
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+
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+ default:
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+ offset = mtk_pwm_reg_offset_v1[channel];
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+ }
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writel(val, priv->base + offset + reg);
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}
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@@ -159,27 +178,38 @@ static const struct pwm_ops mtk_pwm_ops
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static const struct mtk_pwm_soc mt7622_data = {
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.num_pwms = 6,
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.pwm45_fixup = false,
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+ .reg_ver = PWM_REG_V1,
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};
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static const struct mtk_pwm_soc mt7623_data = {
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.num_pwms = 5,
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.pwm45_fixup = true,
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+ .reg_ver = PWM_REG_V1,
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};
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static const struct mtk_pwm_soc mt7629_data = {
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.num_pwms = 1,
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.pwm45_fixup = false,
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+ .reg_ver = PWM_REG_V1,
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+};
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+
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+static const struct mtk_pwm_soc mt7981_data = {
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+ .num_pwms = 2,
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+ .pwm45_fixup = false,
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+ .reg_ver = PWM_REG_V2,
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};
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static const struct mtk_pwm_soc mt7986_data = {
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.num_pwms = 2,
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.pwm45_fixup = false,
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+ .reg_ver = PWM_REG_V1,
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};
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static const struct udevice_id mtk_pwm_ids[] = {
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{ .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data },
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{ .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data },
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{ .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
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+ { .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data },
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{ .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data },
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{ }
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};
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