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87 lines
3.4 KiB
Diff
87 lines
3.4 KiB
Diff
From 010e3665babdf589e26e2fb098ac1f39e519c0f6 Mon Sep 17 00:00:00 2001
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From: Boris Brezillon <boris.brezillon@bootlin.com>
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Date: Fri, 3 Aug 2018 11:22:31 +0200
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Subject: [PATCH] drm/vc4: Fix X/Y positioning of planes using T_TILES
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modifier
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X/Y positioning of T-format buffers is quite tricky and the current
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implementation was failing to position a plane using this format
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correctly when the CRTC X, Y or both X and Y offsets were negative.
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It was also failing when the SRC X/Y offsets were != 0.
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Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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Link: https://patchwork.freedesktop.org/patch/msgid/20180803092231.26446-5-boris.brezillon@bootlin.com
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---
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drivers/gpu/drm/vc4/vc4_plane.c | 50 ++++++++++++++++++++++++++++-----
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1 file changed, 43 insertions(+), 7 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -578,22 +578,58 @@ static int vc4_plane_mode_set(struct drm
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(i ? h_subsample : 1) *
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fb->format->cpp[i];
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}
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+
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break;
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case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
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- /* For T-tiled, the FB pitch is "how many bytes from
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- * one row to the next, such that pitch * tile_h ==
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- * tile_size * tiles_per_row."
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- */
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u32 tile_size_shift = 12; /* T tiles are 4kb */
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+ /* Whole-tile offsets, mostly for setting the pitch. */
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+ u32 tile_w_shift = fb->format->cpp[0] == 2 ? 6 : 5;
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u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
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+ u32 tile_w_mask = (1 << tile_w_shift) - 1;
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+ /* The height mask on 32-bit-per-pixel tiles is 63, i.e. twice
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+ * the height (in pixels) of a 4k tile.
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+ */
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+ u32 tile_h_mask = (2 << tile_h_shift) - 1;
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+ /* For T-tiled, the FB pitch is "how many bytes from one row to
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+ * the next, such that
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+ *
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+ * pitch * tile_h == tile_size * tiles_per_row
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+ */
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u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
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+ u32 tiles_l = vc4_state->src_x >> tile_w_shift;
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+ u32 tiles_r = tiles_w - tiles_l;
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+ u32 tiles_t = vc4_state->src_y >> tile_h_shift;
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+ /* Intra-tile offsets, which modify the base address (the
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+ * SCALER_PITCH0_TILE_Y_OFFSET tells HVS how to walk from that
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+ * base address).
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+ */
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+ u32 tile_y = (vc4_state->src_y >> 4) & 1;
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+ u32 subtile_y = (vc4_state->src_y >> 2) & 3;
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+ u32 utile_y = vc4_state->src_y & 3;
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+ u32 x_off = vc4_state->src_x & tile_w_mask;
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+ u32 y_off = vc4_state->src_y & tile_h_mask;
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tiling = SCALER_CTL0_TILING_256B_OR_T;
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+ pitch0 = (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) |
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+ VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) |
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+ VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) |
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+ VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R));
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+ vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift);
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+ vc4_state->offsets[0] += subtile_y << 8;
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+ vc4_state->offsets[0] += utile_y << 4;
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+
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+ /* Rows of tiles alternate left-to-right and right-to-left. */
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+ if (tiles_t & 1) {
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+ pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR;
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+ vc4_state->offsets[0] += (tiles_w - tiles_l) <<
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+ tile_size_shift;
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+ vc4_state->offsets[0] -= (1 + !tile_y) << 10;
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+ } else {
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+ vc4_state->offsets[0] += tiles_l << tile_size_shift;
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+ vc4_state->offsets[0] += tile_y << 10;
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+ }
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- pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET) |
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- VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L) |
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- VC4_SET_FIELD(tiles_w, SCALER_PITCH0_TILE_WIDTH_R));
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break;
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}
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