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https://github.com/openwrt/openwrt.git
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b4c02c9998
Removed upstreamed patches:
generic/pending-5.4
445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch
446-mtd-spinand-gigadevice-Add-QE-Bit.patch
pistachio/patches-5.4
150-pwm-img-Fix-null-pointer-access-in-probe.patch
Manually rebased:
layerscape/patches-5.4
801-audio-0011-Revert-ASoC-fsl_sai-add-of_match-data.patch
801-audio-0039-MLK-16224-6-ASoC-fsl_sai-fix-DSD-suspend-resume.patch
801-audio-0073-MLK-21957-3-ASoC-fsl_sai-add-bitcount-and-timestamp-.patch
820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh.patch
All modifications made by update_kernel.sh
Build system: x86_64
Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711,
mvebu (mamba, rango), x86_64, ramips/mt7621
Run-tested: ipq806x/R7800, mvebu (mamba, rango), x86_64, ramips (RT-AC57U)
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
[alter 820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
59 lines
1.6 KiB
Diff
59 lines
1.6 KiB
Diff
From 6c37f43308f29a59bc67d4ed010f8fbbf076ec79 Mon Sep 17 00:00:00 2001
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From: popcornmix <popcornmix@gmail.com>
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Date: Tue, 3 Sep 2019 20:28:00 +0100
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Subject: [PATCH] clk-bcm2835: Disable v3d clock
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This is controlled by firmware, see clk-raspberrypi.c
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Signed-off-by: popcornmix <popcornmix@gmail.com>
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---
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drivers/clk/bcm/clk-bcm2835.c | 30 ++++++++++++------------------
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1 file changed, 12 insertions(+), 18 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -1734,16 +1734,12 @@ static const struct bcm2835_clk_desc clk
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.hold_mask = CM_PLLA_HOLDCORE,
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.fixed_divider = 1,
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.flags = CLK_SET_RATE_PARENT),
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- [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
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- SOC_ALL,
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- .name = "plla_per",
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- .source_pll = "plla",
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- .cm_reg = CM_PLLA,
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- .a2w_reg = A2W_PLLA_PER,
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- .load_mask = CM_PLLA_LOADPER,
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- .hold_mask = CM_PLLA_HOLDPER,
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- .fixed_divider = 1,
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- .flags = CLK_SET_RATE_PARENT),
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+
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+ /*
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+ * PLLA_PER is used for gpu clocks. Controlled by firmware, see
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+ * clk-raspberrypi.c.
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+ */
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+
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[BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
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SOC_ALL,
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.name = "plla_dsi0",
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@@ -2021,14 +2017,12 @@ static const struct bcm2835_clk_desc clk
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.int_bits = 6,
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.frac_bits = 0,
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.tcnt_mux = 3),
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- [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
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- SOC_ALL,
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- .name = "v3d",
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- .ctl_reg = CM_V3DCTL,
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- .div_reg = CM_V3DDIV,
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- .int_bits = 4,
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- .frac_bits = 8,
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- .tcnt_mux = 4),
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+
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+ /*
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+ * CLOCK_V3D is used for v3d clock. Controlled by firmware, see
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+ * clk-raspberrypi.c.
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+ */
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+
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/*
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* VPU clock. This doesn't have an enable bit, since it drives
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* the bus for everything else, and is special so it doesn't need
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