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b4c02c9998
Removed upstreamed patches:
generic/pending-5.4
445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch
446-mtd-spinand-gigadevice-Add-QE-Bit.patch
pistachio/patches-5.4
150-pwm-img-Fix-null-pointer-access-in-probe.patch
Manually rebased:
layerscape/patches-5.4
801-audio-0011-Revert-ASoC-fsl_sai-add-of_match-data.patch
801-audio-0039-MLK-16224-6-ASoC-fsl_sai-fix-DSD-suspend-resume.patch
801-audio-0073-MLK-21957-3-ASoC-fsl_sai-add-bitcount-and-timestamp-.patch
820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh.patch
All modifications made by update_kernel.sh
Build system: x86_64
Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711,
mvebu (mamba, rango), x86_64, ramips/mt7621
Run-tested: ipq806x/R7800, mvebu (mamba, rango), x86_64, ramips (RT-AC57U)
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
[alter 820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
54 lines
1.8 KiB
Diff
54 lines
1.8 KiB
Diff
From cfe0832e8306cd9955f682b7314a5a6fc3b9d514 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Thu, 2 May 2019 15:11:05 -0700
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Subject: [PATCH] clk: bcm2835: Add support for setting leaf clock
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rates while running.
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As long as you wait for !BUSY, you can do glitch-free updates of clock
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rate while the clock is running.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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---
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drivers/clk/bcm/clk-bcm2835.c | 22 +++++++++++++---------
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1 file changed, 13 insertions(+), 9 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -1114,15 +1114,19 @@ static int bcm2835_clock_set_rate(struct
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spin_lock(&cprman->regs_lock);
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- /*
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- * Setting up frac support
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- *
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- * In principle it is recommended to stop/start the clock first,
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- * but as we set CLK_SET_RATE_GATE during registration of the
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- * clock this requirement should be take care of by the
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- * clk-framework.
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+ ctl = cprman_read(cprman, data->ctl_reg);
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+
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+ /* If the clock is running, we have to pause clock generation while
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+ * updating the control and div regs. This is glitchless (no clock
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+ * signals generated faster than the rate) but each reg access is two
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+ * OSC cycles so the clock will slow down for a moment.
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*/
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- ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
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+ if (ctl & CM_ENABLE) {
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+ cprman_write(cprman, data->ctl_reg, ctl & ~CM_ENABLE);
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+ bcm2835_clock_wait_busy(clock);
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+ }
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+
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+ ctl &= ~CM_FRAC;
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ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
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cprman_write(cprman, data->ctl_reg, ctl);
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@@ -1494,7 +1498,7 @@ static struct clk_hw *bcm2835_register_c
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init.ops = &bcm2835_vpu_clock_clk_ops;
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} else {
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init.ops = &bcm2835_clock_clk_ops;
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- init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
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+ init.flags |= CLK_SET_PARENT_GATE;
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/* If the clock wasn't actually enabled at boot, it's not
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* critical.
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