openwrt/target/linux/ath79/dts/ar7240_engenius_enh202-v1.dts
Adrian Schmutzler 7054721cf9 ath79: enable UART in SoC DTSI files
The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.

Where the majority of devices is using it, also move the serial0
alias to the DTSI.

*) Since GL-USB150 even defines serial0 alias, the missing uart
   is probably just a mistake. Anyway, disable it for now so this
   patch stays cosmetic.

Apply this to 21.02 as well to remove an unnecessary backporting
pitfall.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
(cherry picked from commit 3a4b751110)
2021-02-25 14:42:11 +01:00

181 lines
3.0 KiB
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "ar7240.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/mtd/partitions/uimage.h>
/ {
compatible = "engenius,enh202-v1", "qca,ar7240";
model = "EnGenius ENH202 v1";
aliases {
led-boot = &led_rssihigh;
led-failsafe = &led_rssihigh;
led-running = &led_rssihigh;
led-upgrade = &led_rssihigh;
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&jtag_disable_pins &switch_led_disable_pins &clks_disable_pins>;
rssilow {
label = "red:rssilow";
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
};
rssimedium {
label = "amber:rssimedium";
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
};
led_rssihigh: rssihigh {
label = "green:rssihigh";
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
};
lan {
label = "amber:lan";
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
wan {
label = "green:wan";
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
};
};
ath9k-leds {
compatible = "gpio-leds";
wlan {
label = "green:wlan";
gpios = <&ath9k 1 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
};
virtual_flash {
compatible = "mtd-concat";
devices = <&fwconcat0 &fwconcat1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
compatible = "openwrt,uimage", "denx,uimage";
openwrt,ih-magic = <IH_MAGIC_OKLI>;
label = "firmware";
reg = <0x0 0x0>;
};
};
};
};
&spi {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "u-boot-env";
reg = <0x40000 0x10000>;
};
partition@50000 {
label = "custom";
reg = <0x50000 0x50000>;
read-only;
};
partition@a0000 {
label = "loader";
reg = <0xa0000 0x10000>;
read-only;
};
fwconcat1: partition@b0000 {
label = "fwconcat1";
reg = <0xb0000 0xf0000>;
};
partition@1a0000 {
label = "fakeroot";
reg = <0x1a0000 0x10000>;
read-only;
};
fwconcat0: partition@1b0000 {
label = "fwconcat0";
reg = <0x1b0000 0x4c0000>;
};
partition@670000 {
label = "failsafe";
reg = <0x670000 0x180000>;
read-only;
};
art: partition@7f0000 {
label = "art";
reg = <0x7f0000 0x10000>;
read-only;
};
};
};
};
&eth0 {
mtd-mac-address = <&art 0x0>;
};
&eth1 {
status = "okay";
mtd-mac-address = <&art 0x0>;
};
&pcie {
status = "okay";
ath9k: wifi@0,0 {
compatible = "pci168c,002a";
reg = <0x0000 0 0 0 0>;
qca,no-eeprom;
#gpio-cells = <2>;
gpio-controller;
};
};