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c11adb4b53
Move v6.11 backported bmips CBR patches from bmips target to generic. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
172 lines
5.0 KiB
Diff
172 lines
5.0 KiB
Diff
From a5c05453a13ab324ad8719e8a23dfb6af01f3652 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Thu, 20 Jun 2024 17:26:42 +0200
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Subject: [PATCH 1/4] mips: bmips: rework and cache CBR addr handling
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Rework the handling of the CBR address and cache it. This address
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doesn't change and can be cached instead of reading the register every
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time.
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This is in preparation of permitting to tweak the CBR address in DT with
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broken SoC or bootloader.
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bmips_cbr_addr is defined in setup.c for each arch to keep compatibility
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with legacy brcm47xx/brcm63xx and generic BMIPS target.
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Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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---
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arch/mips/bcm47xx/prom.c | 3 +++
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arch/mips/bcm47xx/setup.c | 4 ++++
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arch/mips/bcm63xx/prom.c | 3 +++
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arch/mips/bcm63xx/setup.c | 4 ++++
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arch/mips/bmips/dma.c | 2 +-
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arch/mips/bmips/setup.c | 7 ++++++-
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arch/mips/include/asm/bmips.h | 1 +
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arch/mips/kernel/smp-bmips.c | 4 ++--
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8 files changed, 24 insertions(+), 4 deletions(-)
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--- a/arch/mips/bcm47xx/prom.c
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+++ b/arch/mips/bcm47xx/prom.c
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@@ -32,6 +32,7 @@
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#include <linux/ssb/ssb_driver_chipcommon.h>
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#include <linux/ssb/ssb_regs.h>
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#include <linux/smp.h>
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+#include <asm/bmips.h>
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#include <asm/bootinfo.h>
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#include <bcm47xx.h>
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#include <bcm47xx_board.h>
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@@ -109,6 +110,8 @@ static __init void prom_init_mem(void)
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void __init prom_init(void)
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{
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+ /* Cache CBR addr before CPU/DMA setup */
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+ bmips_cbr_addr = BMIPS_GET_CBR();
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prom_init_mem();
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setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0);
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}
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--- a/arch/mips/bcm47xx/setup.c
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+++ b/arch/mips/bcm47xx/setup.c
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@@ -37,6 +37,7 @@
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#include <linux/ssb/ssb.h>
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#include <linux/ssb/ssb_embedded.h>
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#include <linux/bcma/bcma_soc.h>
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+#include <asm/bmips.h>
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#include <asm/bootinfo.h>
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#include <asm/idle.h>
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#include <asm/prom.h>
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@@ -45,6 +46,9 @@
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#include <bcm47xx.h>
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#include <bcm47xx_board.h>
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+/* CBR addr doesn't change and we can cache it */
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+void __iomem *bmips_cbr_addr __read_mostly;
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+
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union bcm47xx_bus bcm47xx_bus;
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EXPORT_SYMBOL(bcm47xx_bus);
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--- a/arch/mips/bcm63xx/prom.c
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+++ b/arch/mips/bcm63xx/prom.c
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@@ -22,6 +22,9 @@ void __init prom_init(void)
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{
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u32 reg, mask;
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+ /* Cache CBR addr before CPU/DMA setup */
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+ bmips_cbr_addr = BMIPS_GET_CBR();
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+
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bcm63xx_cpu_init();
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/* stop any running watchdog */
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--- a/arch/mips/bcm63xx/setup.c
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+++ b/arch/mips/bcm63xx/setup.c
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@@ -12,6 +12,7 @@
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#include <linux/memblock.h>
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#include <linux/ioport.h>
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#include <linux/pm.h>
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+#include <asm/bmips.h>
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#include <asm/bootinfo.h>
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#include <asm/time.h>
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#include <asm/reboot.h>
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@@ -22,6 +23,9 @@
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#include <bcm63xx_io.h>
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#include <bcm63xx_gpio.h>
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+/* CBR addr doesn't change and we can cache it */
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+void __iomem *bmips_cbr_addr __read_mostly;
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+
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void bcm63xx_machine_halt(void)
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{
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pr_info("System halted\n");
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--- a/arch/mips/bmips/dma.c
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+++ b/arch/mips/bmips/dma.c
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@@ -9,7 +9,7 @@ bool bmips_rac_flush_disable;
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void arch_sync_dma_for_cpu_all(void)
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{
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- void __iomem *cbr = BMIPS_GET_CBR();
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+ void __iomem *cbr = bmips_cbr_addr;
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u32 cfg;
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if (boot_cpu_type() != CPU_BMIPS3300 &&
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--- a/arch/mips/bmips/setup.c
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+++ b/arch/mips/bmips/setup.c
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@@ -34,6 +34,9 @@
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#define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
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#define BCM6328_TP1_DISABLED BIT(9)
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+/* CBR addr doesn't change and we can cache it */
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+void __iomem *bmips_cbr_addr __read_mostly;
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+
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extern bool bmips_rac_flush_disable;
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static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
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@@ -111,7 +114,7 @@ static void bcm6358_quirks(void)
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* because the bootloader is not initializing it properly.
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*/
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bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) ||
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- !!BMIPS_GET_CBR();
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+ !!bmips_cbr_addr;
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}
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static void bcm6368_quirks(void)
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@@ -144,6 +147,8 @@ static void __init bmips_init_cfe(void)
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void __init prom_init(void)
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{
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+ /* Cache CBR addr before CPU/DMA setup */
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+ bmips_cbr_addr = BMIPS_GET_CBR();
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bmips_init_cfe();
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bmips_cpu_setup();
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register_bmips_smp_ops();
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--- a/arch/mips/include/asm/bmips.h
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+++ b/arch/mips/include/asm/bmips.h
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@@ -81,6 +81,7 @@ extern char bmips_smp_movevec[];
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extern char bmips_smp_int_vec[];
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extern char bmips_smp_int_vec_end[];
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+extern void __iomem *bmips_cbr_addr;
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extern int bmips_smp_enabled;
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extern int bmips_cpu_offset;
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extern cpumask_t bmips_booted_mask;
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--- a/arch/mips/kernel/smp-bmips.c
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+++ b/arch/mips/kernel/smp-bmips.c
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@@ -518,7 +518,7 @@ static void bmips_set_reset_vec(int cpu,
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info.val = val;
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bmips_set_reset_vec_remote(&info);
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} else {
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- void __iomem *cbr = BMIPS_GET_CBR();
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+ void __iomem *cbr = bmips_cbr_addr;
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if (cpu == 0)
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__raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
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@@ -591,7 +591,7 @@ asmlinkage void __weak plat_wired_tlb_se
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void bmips_cpu_setup(void)
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{
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- void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
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+ void __iomem __maybe_unused *cbr = bmips_cbr_addr;
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u32 __maybe_unused cfg;
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switch (current_cpu_type()) {
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