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22b9f99b87
Drop patch that was superseded upstream: ramips/0036-mtd-fix-cfi-cmdset-0002-erase-status-check.patch Drop upstreamed patches: - apm821xx/020-0001-crypto-crypto4xx-remove-bad-list_del.patch - apm821xx/020-0011-crypto-crypto4xx-fix-crypto4xx_build_pdr-crypto4xx_b.patch - ath79/0011-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch - brcm63xx/001-4.15-08-bcm63xx_enet-correct-clock-usage.patch - brcm63xx/001-4.15-09-bcm63xx_enet-do-not-write-to-random-DMA-channel-on-B.patch - generic/backport/080-net-convert-sock.sk_wmem_alloc-from-atomic_t-to-refc.patch - generic/pending/170-usb-dwc2-Fix-DMA-alignment-to-start-at-allocated-boun.patch - generic/pending/900-gen_stats-fix-netlink-stats-padding.patch In 4.14.55, a patch was introduced that breaks ext4 images in some cases. The newly introduced patch backport-4.14/500-ext4-fix-check-to-prevent-initializing-reserved-inod.patch addresses this breakage. Fixes the following CVEs: - CVE-2018-10876 - CVE-2018-10877 - CVE-2018-10879 - CVE-2018-10880 - CVE-2018-10881 - CVE-2018-10882 - CVE-2018-10883 Compile-tested: ath79, octeon, x86/64 Runtime-tested: ath79, octeon, x86/64 Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
279 lines
7.9 KiB
Diff
279 lines
7.9 KiB
Diff
From 187519403273f0599c848d20eca9acce8b1807a5 Mon Sep 17 00:00:00 2001
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From: Sricharan R <sricharan@codeaurora.org>
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Date: Fri, 25 May 2018 11:41:12 +0530
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Subject: [PATCH] ARM: dts: ipq4019: Add a few peripheral nodes
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Now with the driver updates for some peripherals being there,
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add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
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peripheral support.
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Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
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Signed-off-by: Sricharan R <sricharan@codeaurora.org>
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Signed-off-by: Andy Gross <andy.gross@linaro.org>
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---
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arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +-
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 156 ++++++++++++++++++++++++--
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2 files changed, 146 insertions(+), 12 deletions(-)
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--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
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@@ -61,7 +61,7 @@
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status = "ok";
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};
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- spi_0: spi@78b5000 {
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+ spi@78b5000 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "ok";
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -24,8 +24,10 @@
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interrupt-parent = <&intc>;
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aliases {
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- spi0 = &spi_0;
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- i2c0 = &i2c_0;
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+ spi0 = &blsp1_spi1;
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+ spi1 = &blsp1_spi2;
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+ i2c0 = &blsp1_i2c3;
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+ i2c1 = &blsp1_i2c4;
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};
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cpus {
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@@ -132,6 +134,12 @@
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};
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};
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+ firmware {
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+ scm {
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+ compatible = "qcom,scm-ipq4019";
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+ };
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+ };
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+
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 2 0xf08>,
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@@ -177,13 +185,13 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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- interrupts = <0 208 0>;
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+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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};
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blsp_dma: dma@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x07884000 0x23000>;
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- interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
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+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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@@ -191,7 +199,7 @@
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status = "disabled";
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};
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- spi_0: spi@78b5000 {
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+ blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x78b5000 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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@@ -200,10 +208,26 @@
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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+ dmas = <&blsp_dma 5>, <&blsp_dma 4>;
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+ dma-names = "rx", "tx";
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+ status = "disabled";
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+ };
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+
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+ blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
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+ compatible = "qcom,spi-qup-v2.2.1";
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+ reg = <0x78b6000 0x600>;
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+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
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+ <&gcc GCC_BLSP1_AHB_CLK>;
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+ clock-names = "core", "iface";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ dmas = <&blsp_dma 7>, <&blsp_dma 6>;
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+ dma-names = "rx", "tx";
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status = "disabled";
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};
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- i2c_0: i2c@78b7000 {
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+ blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x78b7000 0x600>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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@@ -212,14 +236,29 @@
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clock-names = "iface", "core";
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#address-cells = <1>;
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#size-cells = <0>;
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+ dmas = <&blsp_dma 9>, <&blsp_dma 8>;
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+ dma-names = "rx", "tx";
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status = "disabled";
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};
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+ blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
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+ compatible = "qcom,i2c-qup-v2.2.1";
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+ reg = <0x78b8000 0x600>;
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+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
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+ clock-names = "iface", "core";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ dmas = <&blsp_dma 11>, <&blsp_dma 10>;
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+ dma-names = "rx", "tx";
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+ status = "disabled";
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+ };
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cryptobam: dma@8e04000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x08e04000 0x20000>;
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- interrupts = <GIC_SPI 207 0>;
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+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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@@ -293,7 +332,7 @@
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serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78af000 0x200>;
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- interrupts = <0 107 0>;
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+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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@@ -305,7 +344,7 @@
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serial@78b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78b0000 0x200>;
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- interrupts = <0 108 0>;
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+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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@@ -327,6 +366,101 @@
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reg = <0x4ab000 0x4>;
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};
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+ pcie0: pci@40000000 {
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+ compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
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+ reg = <0x40000000 0xf1d
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+ 0x40000f20 0xa8
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+ 0x80000 0x2000
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+ 0x40100000 0x1000>;
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+ reg-names = "dbi", "elbi", "parf", "config";
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+ device_type = "pci";
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+ linux,pci-domain = <0>;
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+ bus-range = <0x00 0xff>;
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+ num-lanes = <1>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
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+ 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
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+
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+ interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
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+ interrupt-names = "msi";
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0x7>;
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+ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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+ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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+ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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+ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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+ clocks = <&gcc GCC_PCIE_AHB_CLK>,
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+ <&gcc GCC_PCIE_AXI_M_CLK>,
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+ <&gcc GCC_PCIE_AXI_S_CLK>;
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+ clock-names = "aux",
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+ "master_bus",
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+ "slave_bus";
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+
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+ resets = <&gcc PCIE_AXI_M_ARES>,
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+ <&gcc PCIE_AXI_S_ARES>,
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+ <&gcc PCIE_PIPE_ARES>,
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+ <&gcc PCIE_AXI_M_VMIDMT_ARES>,
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+ <&gcc PCIE_AXI_S_XPU_ARES>,
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+ <&gcc PCIE_PARF_XPU_ARES>,
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+ <&gcc PCIE_PHY_ARES>,
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+ <&gcc PCIE_AXI_M_STICKY_ARES>,
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+ <&gcc PCIE_PIPE_STICKY_ARES>,
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+ <&gcc PCIE_PWR_ARES>,
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+ <&gcc PCIE_AHB_ARES>,
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+ <&gcc PCIE_PHY_AHB_ARES>;
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+ reset-names = "axi_m",
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+ "axi_s",
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+ "pipe",
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+ "axi_m_vmid",
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+ "axi_s_xpu",
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+ "parf",
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+ "phy",
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+ "axi_m_sticky",
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+ "pipe_sticky",
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+ "pwr",
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+ "ahb",
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+ "phy_ahb";
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+
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+ status = "disabled";
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+ };
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+
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+ qpic_bam: dma@7984000 {
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+ compatible = "qcom,bam-v1.7.0";
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+ reg = <0x7984000 0x1a000>;
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+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_QPIC_CLK>;
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+ clock-names = "bam_clk";
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+ #dma-cells = <1>;
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+ qcom,ee = <0>;
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+ status = "disabled";
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+ };
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+
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+ nand: qpic-nand@79b0000 {
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+ compatible = "qcom,ipq4019-nand";
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+ reg = <0x79b0000 0x1000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ clocks = <&gcc GCC_QPIC_CLK>,
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+ <&gcc GCC_QPIC_AHB_CLK>;
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+ clock-names = "core", "aon";
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+
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+ dmas = <&qpic_bam 0>,
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+ <&qpic_bam 1>,
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+ <&qpic_bam 2>;
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+ dma-names = "tx", "rx", "cmd";
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+ status = "disabled";
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+
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+ nand@0 {
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+ reg = <0>;
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+
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+ nand-ecc-strength = <4>;
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+ nand-ecc-step-size = <512>;
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+ nand-bus-width = <8>;
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+ };
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+ };
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+
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wifi0: wifi@a000000 {
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compatible = "qcom,ipq4019-wifi";
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reg = <0xa000000 0x200000>;
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@@ -360,7 +494,7 @@
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<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
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- <GIC_SPI 168 IRQ_TYPE_NONE>;
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+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0", "msi1", "msi2", "msi3",
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"msi4", "msi5", "msi6", "msi7",
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"msi8", "msi9", "msi10", "msi11",
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@@ -402,7 +536,7 @@
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<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
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- <GIC_SPI 169 IRQ_TYPE_NONE>;
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+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0", "msi1", "msi2", "msi3",
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"msi4", "msi5", "msi6", "msi7",
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"msi8", "msi9", "msi10", "msi11",
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