openwrt/target/linux/ath79/dts/ar9344_senao_ap-dual.dtsi
Michael Pratt c107506883 ath79: fix RGMII delay for ar9344 Senao APs
after some trial and error, it was discovered
that by setting TX only delay on the AR8035 PHY
that setting GMAC registers is no longer necessary.

Signed-off-by: Michael Pratt <mcpratt@pm.me>
2022-09-11 21:54:00 +02:00

79 lines
1.2 KiB
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "ar9344.dtsi"
#include "ar934x_senao_loader.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
aliases {
label-mac-device = &eth0;
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
linux,code = <KEY_RESTART>;
};
};
ath9k-leds {
compatible = "gpio-leds";
wifi2g {
label = "blue:wifi2g";
gpios = <&ath9k 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
};
};
&mdio0 {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
eee-broken-100tx;
eee-broken-1000t;
};
};
&eth0 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-txid";
pll-data = <0x02000000 0x00000101 0x00001313>;
};
&pcie {
status = "okay";
ath9k: wifi@0,0,0 {
compatible = "pci168c,0030";
reg = <0x0 0 0 0 0>;
ieee80211-freq-limit = <2402000 2482000>;
qca,no-eeprom;
#gpio-cells = <2>;
gpio-controller;
};
};
&wmac {
status = "okay";
ieee80211-freq-limit = <4900000 5990000>;
mtd-cal-data = <&art 0x1000>;
};