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73eeac49be
In the past few years, we have received several reports about SPI Flash not working properly. This is caused by excessively fast clock frequency. It's really annoying to fix them one by one. Let's reduce these aggressive frequencies to 50 MHz. This is a safe and suggested value in the vendor SDK. Signed-off-by: Shiji Yang <yangshiji66@qq.com>
213 lines
3.4 KiB
Plaintext
213 lines
3.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "mt7620a.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/mtd/partitions/uimage.h>
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/ {
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compatible = "dlink,dwr-118-a1", "ralink,mt7620a-soc";
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model = "D-Link DWR-118 A1";
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aliases {
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led-boot = &led_internet;
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led-failsafe = &led_internet;
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led-upgrade = &led_internet;
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};
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keys {
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compatible = "gpio-keys";
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wps {
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label = "wps";
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gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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reset {
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label = "reset";
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gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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leds {
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compatible = "gpio-leds";
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wan {
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function = LED_FUNCTION_WAN;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
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};
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led_internet: internet {
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label = "green:internet";
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gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
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};
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lan {
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function = LED_FUNCTION_LAN;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
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};
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wlan2g {
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label = "green:wlan2g";
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gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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};
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usb {
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function = LED_FUNCTION_USB;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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trigger-sources = <&ohci_port1>, <&ehci_port1>;
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linux,default-trigger = "usbport";
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};
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};
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gpio_export {
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compatible = "gpio-export";
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#size-cells = <0>;
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usb {
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gpio-export,name = "usb";
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gpio-export,output = <0>;
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gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&gpio3 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <50000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "jboot";
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reg = <0x0 0x10000>;
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read-only;
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};
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partition@10000 {
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compatible = "openwrt,uimage", "denx,uimage";
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openwrt,ih-magic = <IH_MAGIC_OKLI>;
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openwrt,offset = <0x10000>;
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label = "firmware";
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reg = <0x10000 0xfe0000>;
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};
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partition@ff0000 {
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label = "config";
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reg = <0xff0000 0x10000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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eeprom_config_e083: eeprom@e083 {
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reg = <0xe083 0x200>;
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};
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macaddr_config_e496: macaddr@e496 {
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compatible = "mac-base";
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reg = <0xe496 0x6>;
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#nvmem-cell-cells = <1>;
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};
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};
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};
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};
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};
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};
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&ehci {
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status = "okay";
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};
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&ohci {
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status = "okay";
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};
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&state_default {
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default {
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groups = "ephy", "uartf", "spi refclk", "wled";
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function = "gpio";
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};
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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wifi@0,0 {
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reg = <0x0000 0 0 0 0>;
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nvmem-cells = <&eeprom_config_e083>, <&macaddr_config_e496 2>;
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nvmem-cell-names = "eeprom", "mac-address";
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led {
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led-sources = <0>;
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led-active-low;
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};
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};
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};
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ðernet {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
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port@4 {
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status = "okay";
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phy-handle = <&phy4>;
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phy-mode = "rgmii";
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};
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port@5 {
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status = "okay";
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phy-handle = <&phy5>;
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phy-mode = "rgmii";
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};
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mdio-bus {
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status = "okay";
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phy4: ethernet-phy@4 {
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reg = <4>;
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phy-mode = "rgmii-rxid";
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};
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phy5: ethernet-phy@5 {
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reg = <5>;
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phy-mode = "rgmii-rxid";
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};
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};
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};
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&gsw {
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mediatek,port4-gmac;
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mediatek,ephy-base = /bits/ 8 <8>;
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};
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